MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 31

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TRUTH TABLE 2 – CKE
(Notes: 1-4)
NOTE: 1. CKE
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
CKE
H
H
L
L
n-1
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
CKE
that
or NOP commands should be issued on any clock edges occurring during the
commands must be provided during
edge n + 1.
H
H
L
L
n
n
t
is the logic state of CKE at clock edge n; CKE
CKS is met).
Reading or Writing
CURRENT STATE
n
Clock Suspend
Clock Suspend
All Banks Idle
All Banks Idle
Power-Down
Power-Down
is the command registered at clock edge n, and ACTION
Self Refresh
Self Refresh
t
XSR period.
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
See Truth Table 3
AUTO REFRESH
COMMAND
VALID
n-1
X
X
X
X
was the state of CKE at the previous clock edge.
31
n
n
is a result of COMMAND
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ACTION
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
t
XSR period. A minimum of two NOP
256Mb: x4, x8, x16
n
t
XSR is met. COMMAND INHIBIT
n
.
©2002, Micron Technology, Inc.
SDRAM
NOTES
6
5
7