MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 41

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
SYMBOL*
t
t
t
t
t
AH
AS
CH
CL
CK (3)
A0-A9, A11, A12
DQML, DQMU
COMMAND
Precharge all
BA0, BA1
active banks
DQM/
CKE
CLK
A10
DQ
MIN
0.8
1.5
2.5
2.5
7
High-Z
t CMS
t CKS
-7E
t AS
SINGLE BANK
PRECHARGE
ALL BANKS
BANK(S)
T0
MAX
t CMH
t CKH
t AH
Two clock cycles
All banks idle, enter
power-down mode
t CK
MIN
0.8
1.5
2.5
2.5
7.5
T1
NOP
-75
MAX
POWER-DOWN MODE
t CKS
t CL
T2
NOP
UNITS
ns
ns
ns
ns
ns
Input buffers gated off while in
power-down mode
t CH
41
Exit power-down mode
SYMBOL*
t
t
t
t
t
CK (2)
CKH
CKS
CMH
CMS
(
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
MIN
7.5
0.8
1.5
0.8
1.5
-7E
MAX
256Mb: x4, x8, x16
t CKS
Tn + 1
NOP
All banks idle
MIN
0.8
1.5
0.8
1.5
10
-75
Tn + 2
ACTIVE
ROW
ROW
BANK
©2002, Micron Technology, Inc.
MAX
SDRAM
DON’T CARE
UNITS
ns
ns
ns
ns
ns