MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 9

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

PIN DESCRIPTIONS
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0-DQ15
44, 45, 47, 48, 50, 51, 53
23-26, 29-34, 22, 35, 36
2, 5, 8, 11, 44, 47, 50, 53
54-PIN TSOP
6, 12, 46, 52
5, 11, 44, 50
3, 9, 43, 49
16, 17, 18
28, 41, 54
1, 14, 27
15, 39
20, 21
38
37
19
39
40
WE#, CAS#,
x4, x8: DQM
x16: DQML,
SYMBOL
DQ0-DQ7
DQ0-DQ3
BA0, BA1
D Q M U
A0-A12
RAS#
V
V
CKE
CLK
CS#
V
V
NC
DD
SS
DD
SS
Q
Q
x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51
Supply DQ Power: Isolated DQ power to the die for improved noise immunity.
Supply DQ Ground: Isolated DQ ground to the die for improved noise immunity.
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
Input
x8: I/O
x4: I/O
TYPE
Input
Input
Input
Input
Input
Input
–
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a
NC and DQMH is DQM. On the x16, DQML corresponds to DQ0-
DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are
considered same state when referenced as DQM.
Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Address Inputs: A0-A12 are sampled during the ACTIVE command (row-
address A0-A12) and READ/WRITE command (column-address A0-A9, A11
[x4]; A0-A9 [x8]; A0-A8 [x16]; with A10 defining auto precharge) to select
one location out of the memory array in the respective bank. A10 is
sampled during a PRECHARGE command to determine if all banks are to
be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]). The
address inputs also provide the op-code during a LOAD MODE
REGISTER command.
are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs
for x4).
Data Input/Output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
Data Input/Output: Data bus for x4.
No Connect: This pin should be left unconnected.
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
256Mb: x4, x8, x16
©2002, Micron Technology, Inc.
SDRAM