MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 49

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
A0-A9, A11, A12
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
COMMAND
BA0, BA1
DQM/
2. x16: A9, A11, and A12 = “Don’t Care”
A10
CLK
CKE
DQ
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CMS
t CKS
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
t AS
t AS
t AS
7
ACTIVE
BANK 0
T0
ROW
ROW
t CKH
-7E
t CMH
t AH
t AH
t AH
t RCD - BANK 0
t RAS - BANK 0
t
t
MAX
RC - BANK 0
RRD
5.4
5.4
t CK
T1
NOP
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
10
ALTERNATING BANK READ ACCESSES
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
-75
BANK 0
T2
READ
t CMH
MAX
t CH
5.4
6
CAS Latency - BANK 0
UNITS
T3
NOP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t LZ
t AC
49
BANK 3
ACTIVE
T4
ROW
ROW
D
OUT
t OH
t AC
SYMBOL*
t
t
t
t
t
t
t
t
t
m
CMH
CMS
LZ
OH
RAS
RC
RCD
RP
RRD
t RCD - BANK 1
D
T5
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
m + 1
t OH
MIN
t AC
0.8
1.5
37
60
15
15
14
1
3
ENABLE AUTO PRECHARGE
-7E
COLUMN b 2
BANK 3
D
120,000
T6
OUT
READ
MAX
256Mb: x4, x8, x16
1
m + 2
t OH
t AC
CAS Latency - BANK 1
t RP - BANK 0
MIN
D
0.8
1.5
44
66
20
20
15
T7
OUT
NOP
1
3
m + 3
t OH
t AC
-75
120,000
©2002, Micron Technology, Inc.
MAX
SDRAM
BANK 0
T8
ACTIVE
ROW
ROW
DON’T CARE
UNDEFINED
D
OUT
t RCD - BANK 0
t OH
t AC
b
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns