MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 50

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

A0-A9, A11, A12
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
t
t
AC (3)
AC (2)
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
DQM/
CKE
A10
CLK
2. x16: A9, A11, and A12 = “Don’t Care”
3. Page left open; no
DQ
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
t CKS
t CMS
t AS
t AS
t AS
MIN
0.8
1.5
2.5
2.5
7.5
0.8
ACTIVE
BANK
T0
ROW
ROW
7
t CKH
t CMH
t AH
t AH
t AH
-7E
t RCD
t CL
MAX
5.4
5.4
T1
NOP
t CH
t
RP.
t CMS
MIN
t CK
0.8
1.5
2.5
2.5
7.5
0.8
10
COLUMN m 2
T2
BANK
READ
t CMH
-75
CAS Latency
READ – FULL-PAGE BURST
MAX
5.4
6
T3
NOP
t LZ
t AC
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
T4
D
NOP
OUT
t OH
50
m
1,024 (x8) locations within same row
2,048 (x4) locations within same row
t AC
512 (x16) locations within same row
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
SYMBOL*
t
t
t
t
t
t
t
t
CKS
CMH
CMS
HZ (3)
HZ (2)
LZ
OH
RCD
D
T5
OUT
NOP
t OH
m+1
Full page completed
t AC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
T6
MIN
OUT
NOP
1.5
0.8
1.5
15
1
1
3
t OH
t AC
m+2
(
(
(
(
(
(
)
(
)
(
)
(
)
(
(
)
)
)
)
)
)
)
(
(
(
(
)
(
)
(
)
(
(
(
(
(
-7E
(
)
(
)
(
)
(
)
(
(
)
)
)
)
(
(
(
)
)
)
)
)
)
(
)
(
)
(
)
)
)
)
MAX
Tn + 1
256Mb: x4, x8, x16
D
5.4
5.4
NOP
OUT
t OH
m-1
t AC
BURST TERM
MIN
Tn + 2
3
1.5
0.8
1.5
20
1
3
Dout m
t OH
-75
t AC
©2002, Micron Technology, Inc.
MAX
SDRAM
5.4
Tn + 3
6
D
OUT
NOP
DON’T CARE
UNDEFINED
t OH
m+1
t HZ
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
Tn + 4
NOP