MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 53

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
SYMBOL*
t
t
t
t
t
t
t
t
t
A0-A9, A11, A12
AH
AS
CH
CL
CK (3)
CK (2)
CKH
CKS
CMH
DQML, DQMU
COMMAND
BA0, BA1
2. x16: A9, A11, and A12 = “Don’t Care”
DQM/
CLK
CKE
A10
DQ
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
MIN
t CMS
t CKS
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
7
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CMH
-7E
t CKH
t AH
t AH
t AH
t RCD
t RAS
t RC
MAX
t CK
T1
NOP
ENABLE AUTO PRECHARGE
MIN
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
10
t CMS
t CL
t DS
COLUMN
WRITE – WITH AUTO PRECHARGE
-75
WRITE
T2
BANK
D
IN
t CMH
t CH
t DH
m
m
MAX
2
t DS
D
IN
T3
NOP
m + 1
UNITS
t DH
ns
ns
ns
ns
ns
ns
ns
ns
ns
t DS
D
IN
T4
NOP
53
m + 2
t DH
SYMBOL*
t
t
t
t
t
t
t
t
CMS
DH
DS
RAS
RC
RCD
RP
WR
t DS
D
IN
T5
NOP
m + 3
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t WR
1 CLK +
MIN
7ns
1.5
0.8
1.5
37
60
15
15
NOP
T6
-7E
1
120,000
MAX
256Mb: x4, x8, x16
T7
NOP
1 CLK +
MIN
7.5ns
1.5
0.8
1.5
44
66
20
20
t RP
NOP
T8
-75
120,000
©2002, Micron Technology, Inc.
MAX
SDRAM
ACTIVE
ROW
ROW
BANK
T9
DON’T CARE
UNITS
ns
ns
ns
ns
ns
ns
ns
–