MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 4

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

256 Mb SDRAM PART NUMBERS
*Actual FBGA part marking shown on page 58.
GENERAL DESCRIPTION
dynamic
268,435,456 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 67,108,864-bit banks is orga-
nized
4 bits. Each of the x8’s 67,108,864-bit banks is orga-
nized as 8,192 rows by 1,024 columns by 8 bits. Each of
the x16’s 67,108,864-bit banks is organized as 8,192
rows by 512 columns by 16 bits.
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
PART NUMBER
MT48LC64M4A2TG
MT48LC64M4A2FB*
MT48LC32M8A2TG
MT48LC32M8A2FB*
MT48LC16M16A2TG
MT48LC16M16A2FG
The 256Mb SDRAM is a high-speed CMOS,
Read and write accesses to the SDRAM are burst
as
random-access
8,192
rows
ARCHITECTURE
64 Meg x 4
64 Meg x 4
32 Meg x 8
32 Meg x 8
16 Meg x 16
16 Meg x 16
by
memory
2,048
columns
54-pin TSOP II
54-ball FBGA
54-pin TSOP II
54-pin TSOP II
60-ball FBGA
60-ball FBGA
PACKAGE
containing
by
4
to select the bank and row to be accessed (BA0, BA1
select the bank; A0–A12 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
chitecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All in-
puts and outputs are LVTTL-compatible.
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
The SDRAM provides for programmable READ or
The 256Mb SDRAM uses an internal pipelined ar-
The 256Mb SDRAM is designed to operate in 3.3V
SDRAMs offer substantial advances in DRAM oper-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16
©2002, Micron Technology, Inc.
SDRAM