MT48LC64M4A2 Micron Technology, MT48LC64M4A2 Datasheet - Page 57

• Manufacturer Part Number: MT48LC64M4A2
• Description: (MT48Lxxxx) SYNCHRONOUS DRAM
• Manufacturer: Micron Technology

A0-A9, A11, A12
TIMING PARAMETERS
*CAS latency indicated in parentheses.
NOTE: 1. x16: A9, A11, and A12 = “Don’t Care”
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
DQML, DQMU
SYMBOL*
t
t
t
t
t
t
t
AH
AS
CH
CL
CK (3)
CK (2)
CKH
COMMAND
BA0, BA1
DQM/
2.
3. Page left open; no
CLK
CKE
A10
DQ
t
WR must be satisfied prior to PRECHARGE command.
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
MIN
t CMS
0.8
1.5
2.5
2.5
7.5
0.8
t CKS
7
t AS
t AS
t AS
ACTIVE
BANK
T0
ROW
ROW
-7E
t CKH
t CMH
t AH
t AH
t AH
MAX
t RCD
t CL
t
RP.
T1
NOP
MIN
t CH
0.8
1.5
2.5
2.5
7.5
0.8
10
-75
t CMS
t CK
t DS
COLUMN
MAX
WRITE – FULL-PAGE BURST
T2
WRITE
BANK
D
IN
t CMH
t DH
m
m
1
UNITS
ns
ns
ns
ns
ns
ns
ns
t DS
D
IN
T3
NOP
m + 1
t DH
57
1,024 (x8) locations within same row
2,048 (x4) locations within same row
512 (x16) locations within same row
t DS
SYMBOL*
t
t
t
t
t
t
CKS
CMH
CMS
DH
DS
RCD
D
IN
T4
NOP
m + 2
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Full page completed
MIN
t DS
1.5
0.8
1.5
0.8
1.5
15
D
IN
T5
NOP
m + 3
-7E
t DH
(
(
(
(
(
MAX
(
)
(
)
(
)
(
)
(
)
256Mb: x4, x8, x16
(
)
)
)
)
)
(
(
(
)
(
(
(
(
(
(
)
(
)
)
(
)
(
)
(
)
(
)
(
)
)
)
(
)
)
)
)
)
(
(
)
(
)
)
(
(
)
)
)
t DS
D
Tn + 1
IN
NOP
m - 1
t DH
Full-page burst does
not self-terminate.
Can use BURST TERMINATE
command to stop.
MIN
1.5
0.8
1.5
0.8
1.5
20
-75
BURST TERM
Tn + 2
©2002, Micron Technology, Inc.
MAX
SDRAM
2, 3
DON’T CARE
UNITS
ns
ns
ns
ns
ns
ns
Tn + 3
NOP