XC3030L

Manufacturer Part NumberXC3030L
DescriptionLogic Cell Array Families
ManufacturerXilinx
XC3030L datasheet
 


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XC3000 Logic Cell Array Families
Overview .............................................................. 2-104
XC3000, XC3000A, XC3000L, XC3100, XC3100A
Logic Cell Array Families ................................. 2-105
Architecture ...................................................... 2-106
Programmable Interconnect ............................. 2-111
Crystal Oscillator .............................................. 2-117
Programming ................................................... 2-118
Special Configuration Functions ...................... 2-122
Master Serial Mode .......................................... 2-124
Master Serial Mode Programming
Switching Characteristics ............................. 2-125
Master Parallel Mode ....................................... 2-126
Master Parallel Mode Programming
Switching Characteristics ............................. 2-127
Peripheral Mode ............................................... 2-128
Peripheral Mode Programming
Switching Characteristics ............................. 2-129
Slave Serial Mode ............................................ 2-130
Slave Serial Mode Programming
Switching Characteristics ............................. 2-131
Program Readback Switching
Characteristics ............................................. 2-131
General LCA Switching Characteristics ........... 2-132
Performance .................................................... 2-133
Power ............................................................... 2-134
Pin Descriptions ............................................... 2-136
Pin Functions During Configuration.................. 2-138
XC3000 Families Pin Assignments .................. 2-139
XC3000 Families Pinouts ................................. 2-140
Component Availability ..................................... 2-151
Ordering Information ........................................ 2-152
XC3000 Logic Cell Array Family ........................... 2-153
Absolute Maximum Ratings ............................. 2-154
Operating Conditions ....................................... 2-154
DC Characteristics ........................................... 2-155
Switching Characteristic Guidelines
CLB .............................................................. 2-156
Buffer ........................................................... 2-156
IOB .............................................................. 2-158
Ordering Information ........................................ 2-160
Component Availability ..................................... 2-160
Table of Contents
XC3000A Logic Cell Array Familiy ....................... 2-161
Absolute Maximum Ratings ............................. 2-162
Operating Conditions ....................................... 2-162
DC Characteristics ........................................... 2-163
Switching Characteristic Guidelines
CLB .............................................................. 2-164
Buffer ........................................................... 2-164
IOB .............................................................. 2-166
Ordering Information ........................................ 2-168
Component Availability ..................................... 2-168
XC3000L Low Voltage Logic Cell Array Family .... 2-169
Absolute Maximum Ratings ............................. 2-170
Operating Conditions ....................................... 2-170
DC Characteristics ........................................... 2-171
Switching Characteristic Guidelines
CLB .............................................................. 2-172
Buffer ........................................................... 2-172
IOB .............................................................. 2-174
Ordering Information ........................................ 2-176
Component Availability ..................................... 2-176
XC3100, XC3100A Logic Cell Array Families ....... 2-177
Absolute Maximum Ratings ............................. 2-178
Operating Conditions ....................................... 2-178
DC Characteristics ........................................... 2-179
Switching Characteristic Guidelines
CLB .............................................................. 2-180
Buffer ........................................................... 2-180
IOB .............................................................. 2-182
Ordering Information ........................................ 2-184
Component Availability ..................................... 2-184
2-103

XC3030L Summary of contents

  • Page 1

    XC3000 Logic Cell Array Families Overview .............................................................. 2-104 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families ................................. 2-105 Architecture ...................................................... 2-106 Programmable Interconnect ............................. 2-111 Crystal Oscillator .............................................. 2-117 Programming ................................................... 2-118 Special Configuration Functions ...................... 2-122 Master Serial ...

  • Page 2

    ... XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Overview Introduced in 1987/88, XC3000 is the industry’s most successful family of FPGAs, with over 10 million devices shipped. In 1992/93, Xilinx introduced three additional families, offering more speed, functionality, and a new supply-voltage option. There are now five distinct family groupings within the XC3000 class of LCA devices. • ...

  • Page 3

    IMPORTANT NOTICE All new designs should use XC3000A or XC3100A. Information on XC3000 and XC3100 is presented here as reference for existing designs. Features • Complete line of five related Field Programmable Gate Array product families – XC3000, XC3000A, XC3000L, ...

  • Page 4

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families The XC3000 Logic Cell Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades. Architecture The perimeter of configurable IOBs provides a pro- grammable interface between ...

  • Page 5

    Read or Write Data Figure 2. Static Configuration Memory Cell loaded with one bit of configuration program and controls one program selection in the Logic Cell Array. The memory cell outputs Q and Q use ground and V ...

  • Page 6

    ... Low - level transparent and vice versa ( falling edge, High transparent). All Xilinx primitives in the supported schematic-entry packages, however, are positive edge- triggered flip-flops or High transparent latches. When one ...

  • Page 7

    Configurable Logic Block The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. The XC3020 has 64 such blocks arranged in 8 ...

  • Page 8

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Any Function Variables Any Function Variables ...

  • Page 9

    RD which, when enabled and High, is dominant over clocked inputs. All flip-flops are reset by the active-Low chip input, RESET, or during the configuration process. The flip-flops share the enable clock (EC) which, when Low, recirculates the flip-flops’ ...

  • Page 10

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Figure 8. XACT Development System Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs ...

  • Page 11

    Figure 9. LCA General-Purpose Interconnect. Composed of a grid of metal segments that may be intercon- nected through switch matrices to form networks for CLB and IOB inputs and outputs ...

  • Page 12

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Figure 12. XC3020 Die-Edge IOBs. The XC3020 die-edge IOBs are provided with direct access to adjacent CLBs. 2-114 X2660 ...

  • Page 13

    Where logic blocks are adjacent to IOBs, direct connect is provided alternately to the IOB inputs (I) and outputs (O) on all four edges of the ...

  • Page 14

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Control of the 3-state input by the same signal that drives the buffer input, creates an open-drain wired-AND func- tion. A logic High on both buffer inputs creates a high impedance, ...

  • Page 15

    Each horizontal Longline is also driven by a weak keeper circuit that prevents undefined floating levels by maintaining the pre- vious logic level when the line is not driven by an active buffer ...

  • Page 16

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Suggested Component Values R1 0.5 – – (may be required for low frequency, phase)t (shift and/or compensation level for crystal Q) C1 – ...

  • Page 17

    Figure 18 shows the state sequences. At the end of Initialization, the LCA device enters the Clear state where it clears the configuration memory. The active ...

  • Page 18

    ... Configuration Data Frames (Each Frame Consists of: A Start Bit (0) A 71-Bit Data Field Three Stop Bits Postamble Code (4 Bits Minimum) XC3020 XC3030 XC3042 XC3020A XC3030A XC3042A XC3020L XC3030L XC3042L XC3120 XC3130 XC3142 XC3120A XC3130A XC3142A 1,000 to 1,500 to 2,000 to 1,500 2,000 ...

  • Page 19

    ... The different LCA devices have different sizes and numbers of data frames. To maintain compatibil- ity between various device types, the Xilinx product fami- lies use compatible configuration formats. For the XC3020, configuration requires 14779 bits for each de- vice, arranged in 197 data frames ...

  • Page 20

    ... Master Serial mode uses serial configura- tion data supplied to Data-in (DIN) from a synchronous serial source such as the Xilinx Serial Configuration PROM shown in Figure 21. Master Parallel Low and High modes automatically use parallel data supplied to the D0–D7 pins in response to the 16-bit address generated by the LCA device ...

  • Page 21

    IOB pull- up resistors in the Operational mode to act either as an input load or to avoid a floating input on an otherwise unused pin. Readback The contents of a Logic ...

  • Page 22

    ... Figure 21. Master Serial Mode In Master Serial mode, the CCLK output of the lead LCA device drives a Xilinx Serial PROM that feeds the LCA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. This puts the next data bit on the SPROM data output, connected to the LCA DIN pin ...

  • Page 23

    Master Serial Mode Programming Switching Characteristics CCLK (Output) 1 Serial Data In Serial DOUT n – 3 (Output) Description CCLK Data In setup Data In hold Notes power-up, V must rise from 2 delayed ...

  • Page 24

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Master Parallel Mode * * + Readback is Activated, a 5-kΩ Resistor is M0 M1PWRDWN Required in Series With M1 5 kΩ CCLK DOUT M2 HDC RCLK ...

  • Page 25

    Master Parallel Mode Programming Switching Characteristics A0-A15 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description RCLK To address valid To data setup To data hold RCLK High RCLK Low Notes power-up, V must rise from 2.0 V ...

  • Page 26

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Peripheral Mode CONTROL ADDRESS SIGNALS BUS +5 V REPROGRAM Figure 23. Peripheral Mode. Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS ...

  • Page 27

    Peripheral Mode Programming Switching Characteristics WRITE TO LCA WS, CS0, CS1 CS2 D0-D7 CCLK RDY/BUSY DOUT Description Write Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required DIN Hold time required RDY/BUSY delay after end ...

  • Page 28

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Slave Serial Mode Micro Computer STRB D0 D1 I/O D2 Port RESET Figure 24. Slave Serial Mode. In Slave Serial mode, an external signal drives the ...

  • Page 29

    Slave Serial Mode Programming Switching Characteristics DIN 1 T DCC CCLK DOUT (Output) Description CCLK To DOUT DIN setup DIN hold High time Low time (Note 1) Frequency Notes: 1. The max limit of CCLK Low time is caused by ...

  • Page 30

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families General LCA Switching Characteristics RESET M0/M1/ DONE/PROG INIT User State (Output) PWRDWN V (Valid) CC Description RESET (2) M0, M1, M2 setup time required M0, M1, ...

  • Page 31

    Performance Device Performance The XC3000 families of FPGAs can achieve very high performance. This is the result of • A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. • Careful optimization of transistor ...

  • Page 32

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families 1.00 0.80 0.60 0.40 0.20 – 55 – 40 – 20 Figure 26. Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations 300 250 200 150 100 XC3100-3 ...

  • Page 33

    One CLB driving three local interconnects One global clock buffer and clock line One device output with load Power Consumption The Logic Cell Array exhibits the low power consumption characteristic of CMOS ICs. For any design, the ...

  • Page 34

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Pin Descriptions Permanently Dedicated Pins Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on ...

  • Page 35

    User I/O Pins that can have special functions. M2 During configuration, this input has a weak pull-up resistor. Together with M0 and M1 sampled before the start of configuration to establish the configuration mode to be used. After ...

  • Page 36

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Configuration Mode <M2:M1:M0> SLAVE MASTER-SER PERIPHERAL <1:1:1> <0:0:0> <1:0:1> PWRDWN (I) PWRDWN (I) PWRDWN (I) VCC VCC VCC M1 (HIGH) (I) M1 (LOW) (I) M1 (LOW) (I) M0 (HIGH) (I) M0 ...

  • Page 37

    ... XC3000 Families Pin Assignments Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 223. Each chip is offered in several package types to accommo- date the available PC board space and manufacturing technology ...

  • Page 38

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin No. XC3030 1 GND 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 PWRDWN 8 TCLKIN-I/O 9 I/O ...

  • Page 39

    XC3000 Families 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts 68 PLCC XC3020 XC3030 XC3020 XC3030, XC3042 10 10 PWRDN 11 11 TCLKIN-I/O 12 — ...

  • Page 40

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3064/XC3090/XC3195 84-Pin PLCC Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PLCC Pin Number XC3064, XC3090, XC3195 12 PWRDN 13 TCLKIN-I/O 14 I/O 15 I/O 16 I/O 17 ...

  • Page 41

    XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin No. XC3020 TQFP XC3030 CQFP PQFP XC3042 VQFP GND A13-I A6-I A12-I A7-I/O 6 ...

  • Page 42

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000 Families 132-Pin Ceramic and Plastic PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts XC3042 PGA Pin PGA Pin XC3064 Number Number GND C4 B13 A1 PWRDN ...

  • Page 43

    XC3000 Families 144-Pin Plastic TQFP Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts XC3042 Pin XC3064 Number 1 PWRDN 2 I/O-TCLKIN 3 I/O* 4 I/O 5 I/O 6 I/O* 7 I/O 8 I/O 9 I/O* 10 I/O ...

  • Page 44

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PQFP PQFP XC3064, XC3090, Pin Number XC3195 Pin Number * 1 I I ...

  • Page 45

    XC3000 Families 175-Pin Ceramic and Plastic PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PGA Pin PGA Pin XC3090, XC3195 Number Number B2 PWRDN D13 D4 TCLKIN-I/O B14 C14 B3 I/O B15 C4 I/O D14 B4 ...

  • Page 46

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin Number XC3090 1 PWRDWN 2 TCLKIN-I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O ...

  • Page 47

    XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin Number Number XC3090 1 – 2 GND 3 PWRDWN 4 TCLKIN-I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O ...

  • Page 48

    XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Pin Description PG223 PQ208 A9-I/O B1 206 A10-I/O E3 205 I/O E4 204 I/O C2 203 I/O C1 202 I/O D2 201 A8-I/O E2 200 A11-I/O F4 199 I/O F3 198 ...

  • Page 49

    ... C C XC3030A - XC3042A - XC3064A - XC3090A - XC3020L C XC3030L C C XC3042L C XC3064L C XC3090L XC3120A - ...

  • Page 50

    ... Bitstream error checking protects against erroneous configuration. Each Xilinx FPGA bitstream consists of a 40-bit preamble, followed by a device-specific number of data frames. The number of bits per frame is also device-specific; however, each frame ends with three stop bits (111) followed by a start bit for the next frame (0) ...