XC3030L Xilinx, XC3030L Datasheet - Page 42

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-rate limited.
* Indicates unconnected package pins (14) for the XC3042.
PGA Pin
Number
A10
B10
A11
C10
B11
A12
B12
A13
C12
C4
A1
C3
B2
B3
A2
B4
C5
A3
A4
B5
C6
A5
B6
A6
B7
C7
C8
A7
B8
A8
A9
B9
C9
I/O-TCLKIN
PWRDN
XC3042
XC3064
GND
GND
VCC
I/O*
I/O*
I/O*
I/O*
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
XC3000 Families 132-Pin Ceramic and Plastic PGA Pinouts
PGA Pin
Number
G13
G14
G12
M14
M13
B13
C11
A14
D12
C13
B14
C14
E12
D13
D14
E13
F12
E14
F13
F14
H12
H14
H13
K14
K13
L14
L13
K12
N14
L12
J14
J13
J12
XTL2(IN)-I/O
XC3042
XC3064
HDC-I/O
LDC-I/O
INIT-I/O
M1-RD
M0-RT
M2-I/O
GND
GND
GND
VCC
VCC
I/O*
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2-144
PGA Pin
Number
M11
M12
M10
P14
N13
P13
N12
P12
N11
P11
N10
P10
M9
N9
N8
M8
M7
N7
N6
M6
N5
M5
N4
N3
N2
P9
P8
P7
P6
P5
P4
P3
P2
RDY/BUSY-RCLK-I/O
XTL1-I/O-BCLKIN
D0-DIN-I/O
DONE-PG
XC3042
XC3064
CS0-I/O
CS1-I/O
RESET
D7-I/O
D6-I/O
D5-I/O
D4-I/O
D3-I/O
D2-I/O
D1-I/O
VCC
VCC
GND
I/O
I/O*
I/O
I/O*
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
*
*
PGA Pin
Number
M3
M4
P1
M2
N1
M1
K3
K2
K1
H1
H2
H3
G3
G2
G1
E1
E2
D1
D2
E3
C1
B1
C2
D3
L3
L2
L1
J3
J2
J1
F1
F2
F3
A1-CS2-I/O
A0-WS-I/O
DOUT-I/O
XC3042
XC3064
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A2-I/O
A3-I/O
A4-I/O
A5-I/O
A6-I/O
A7-I/O
A8-I/O
A9-I/O
CCLK
VCC
GND
GND
VCC
VCC
I/O
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
*