XC3030L Xilinx, XC3030L Datasheet - Page 5

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

Figure 3. Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice of two
clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable. A clock line that
triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can
only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds.
The memory cell outputs Q and Q use ground and V
levels and provide continuous, direct control. The addi-
tional capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
Figure 2. Static Configuration Memory Cell.
It is loaded with one bit of configuration program and
controls one program selection in the Logic Cell Array.
Read or
Write
Data
(OUTPUT ENABLE)
REGISTERED IN
DIRECT IN
3- STATE
OUT
PROGRAM
CONTROLLED
MULTIPLEXER
T
O
I
Q
INVERT
OUT
Q
Q
OK
Configuration
Control
PROGRAM-CONTROLLED MEMORY CELLS
3-STATE
X5382
INVERT
IK
=
PROGRAMMABLE INTERCONNECTION POINT or PIP
LATCH
D
FLOP
Q
FLOP
FLIP
FLIP
R
or
R
CC
Q
D
2-107
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing
information, embedded in the program data by the XACT
development system, to direct memory-cell loading. The
serial-data framing and length-count preamble provide
programming compatibility for mixes of various LCA device
devices in a synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in Figure 3, provides
an interface between the external package pin of the
device and the internal user logic. Each IOB includes both
registered and direct input paths. Each IOB provides a
programmable 3-state output buffer, which may be driven
by a registered or direct output signal. Configuration
options allow each IOB an inversion, a controlled slew rate
and a high impedance pull-up. Each input circuit also
provides input clamping diodes to provide electrostatic
protection, and circuits to inhibit latch-up produced by
input currents.
OUTPUT
SELECT
THRESHOLD
TTL or
CMOS
INPUT
SLEW
RATE
OUTPUT
BUFFER
PASSIVE
PULL UP
(GLOBAL RESET)
CK1
CK2
Vcc
I/O PAD
X3029