XC3030L Xilinx, XC3030L Datasheet - Page 27

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

Peripheral Mode Programming Switching Characteristics
Notes:
go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immedi-
ately after the end of BUSY.
This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will
Write
RDY
1. At power-up, V
2. Configuration must be delayed until the INIT of all LCAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
4. CCLK and DOUT timing is tested in slave mode.
5. T
delayed by holding RESET Low until V
>100 ms, or a non-monotonically rising V
on RESET and D/P after V
the phase of the internal timing generator for CCLK.
T
word is loaded into the input register before the second-level buffer has started shifting out data.
BUSY
BUSY
WS, CS0, CS1
indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T
RDY/BUSY
Effective Write time required
(Assertion of CS0, CS1, CS2, WS)
DIN Setup time required
DIN Hold time required
RDY/BUSY delay after end of WS
Earliest next WS after end of BUSY
BUSY Low time generated
D0-D7
DOUT
CCLK
CS2
CC
must rise from 2.0 V to V
Description
WRITE TO LCA
CC
has reached 4.0 V (2.5 V for the XC3000L).
T
CA
4
1
2
T
Valid
T
DC
WTRB
CC
CC
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
may require a >6- s High level on RESET, followed by a >6- s Low level
min in less than 25 ms. If this is not possible, configuration can be
T
CD
2-129
3
T
BUSY
1
2
4
5
6
3
D6
Symbol
6
Previous Byte
T
T
T
T
T
T
CA
DC
CD
WTRB
RBWT
BUSY
D7
100
D0
Min
60
0
0
2.5
D1
New Byte
BUSY
occurs when a new
D2
Max
60
X3249
CC
9
rise time of
Units
CCLK
Periods
ns
ns
ns
ns
ns