XC3030L Xilinx, XC3030L Datasheet - Page 24

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Master Parallel Mode
Figure 22. Master Parallel Mode
In Master Parallel mode, the lead LCA device directly
addresses an industry-standard byte-wide EPROM and
accepts eight data bits right before incrementing (or
decrementing) the address outputs.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data (and all data that
overflows the lead device) on the DOUT pin. There is an
*
5-kΩ Resistor is
Series With M1
If Readback is
Activated, a
Required in
System Reset
Reprogram
5 kΩ
General-
Purpose
User I/O
+5 V
Pins
RESET
M2
HDC
RCLK
D7
D6
D5
D4
D3
D2
D1
D0
Other
I/O Pins
M0 M1PWRDWN
*
Master
LCA
+5 V
DOUT
CCLK
INIT
A15
A14
A13
A12
A11
A10
D/P
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
N.C.
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
CE
EPROM
8
D7
D6
D5
D4
D3
D2
D1
D0
Collector
2-126
Open
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data, and also changes the
EPROM address, until the falling CCLK edge that makes
the LSB (D0) of this byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy chain accepts data on the subse-
quent rising CCLK edge.
+5 V
CCLK
DIN
D/P
RESET
M0 M1PWRDWN
*
Slave #1
LCA
I/O Pins
Other
DOUT
HDC
LDC
INIT
M2
5 kΩ
General-
Purpose
User I/O
Pins
...
+5 V
CCLK
DIN
D/P
Reset
M0 M1PWRDWN
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
*
Slave #n
5 kΩ Each
LCA
+5 V
I/O Pins
Other
DOUT
HDC
LDC
INIT
M2
5 kΩ
General-
Purpose
User I/O
Pins
X3159