M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 133

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock asynchronous serial I/O (UART) mode
130
Figure 1.16.19. Typical receive timing in UART mode
Figure 1.16.20. Timing for switching serial data logic
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
(a) Sleep mode (UART0, UART1)
(b) Function for switching serial data logic (UART2)
Receive
complete flag
BRGi count
source
Receive enable bit
RxDi
Transfer clock
RTSi
Receive interrupt
request bit
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A0
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
When the data logic select bit (bit 6 of address 037D
transmission buffer register or reading the reception buffer register. Figure 1.16.20 shows the ex-
ample of timing for switching serial data logic.
Transfer clock
16
• When LSB first, parity enabled, one stop bit
, 03A8
(no reverse)
(reverse)
TxD
TxD
16
“1”
“0”
“1”
“0”
“L”
“1”
“0”
“H”
2
2
) is set to “1” during reception. In this mode, the unit performs receive operation when
The above timing applies to the following settings :
Reception triggered when transfer clock
is generated by falling edge of start bit
•Parity is disabled.
•One stop bit.
•RTS function is selected.
“H”
“H”
“H”
“L”
“L”
“L”
Start bit
ST
ST
Sampled “L”
D0
D0
D1
D1
Cleared to “0” when interrupt request is accepted, or cleared by software
D2
D2
D
0
Receive data taken in
D3
D3
Transferred from UARTi receive register to
UARTi receive buffer register
16
) is assigned 1, data is inverted in writing to the
D4
D4
D
D5
D5
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D6
D6
D
7
D7
D7
ST : Start bit
P : Even parity
SP : Stop bit
Stop bit
P
P
SP
SP
M16C / 62A Group
Mitsubishi microcomputers