M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 34

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bus Control
Table 1.9.5. Microcomputer status in wait state (Note)
Note: The RDY signal cannot be received immediately prior to a software wait.
Figure 1.9.4. Example of RD signal extended by RDY signal
(5) The RDY signal
Oscillation
R/W signal, address bus, data bus, CS
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in
Figure 1.9.4, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If
an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5
shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example
in which the RD signal is prolonged by the RDY signal.
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
chip select control register (address 0008
all bits 4 to 7 of the chip select control register (address 0008
properly as in non-using.
___
________
________
________
__________
____
In an instance of separate bus
In an instance of multiplexed bus
BCLK
RD
CS
(i=0 to 3)
RDY
BCLK
RD
CS
(i=0 to 3)
RDY
i
i
: Wait using software
: Wait using RDY signal
Item
_____
________
Accept timing of RDY signal
_____
________
tsu(RDY - BCLK)
16
________
) are set to “0”. The RDY signal is invalid when setting “1” to
________
On
Maintain status when RDY signal received
On
Accept timing of RDY signal
tsu(RDY - BCLK)
16
________
), but the RDY pin should be treated as
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status
________
________
M16C / 62A Group
Mitsubishi microcomputers
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