M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 71

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

DMAC
68
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
Table 1.13.1. DMAC specifications
Reload timing for forward ad-
dress pointer and transfer
counter
No. of channels
Transfer memory space
Maximum No. of bytes transferred
DMA request factors (Note)
Channel priority
Transfer unit
Transfer address direction
Transfer mode
DMA interrupt request generation timing When an underflow occurs in the transfer counter
Active
Writing to register
Reading the register
Inactive
flag (I flag) nor by the interrupt priority level.
Item
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
Falling edge of INT0 or INT1 or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer and reception interrupt requests
UART1 transfer and reception interrupt requests
UART2 transfer and reception interrupt requests
Serial I/O3, 4 interrpt requests
A-D conversion interrupt requests
Software triggers
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
8 bits or 16 bits
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
• Single transfer mode
• Repeat transfer mode
When the DMA enable bit is set to “1”, the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
• When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active, the
value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer, and the value
of the transfer counter reload register is reloaded to the transfer counter.
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
(Note that DMA-related registers [0020
After the transfer counter underflows, the DMA enable bit turns to
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
“0”, and the DMAC turns inactive
________
________
Specification
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
to 003F
16
] cannot be accessed)
M16C / 62A Group
Mitsubishi microcomputers