M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 55

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt
52
Table 1.11.3. Settings of interrupt priority
Interrupt Enable Flag (I flag)
Interrupt Request Bit
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Interrupt priority
level select bit
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to “0” by hardware. The
interrupt request bit can also be set to “0” by software. (Do not set this bit to “1”).
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt levels
enabled, according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = “1”
· interrupt request bit = “1”
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
0
0
0
1
1
1
1
b2 b1 b0
0
0
0
1
0
0
1
1
1
0
1
0
0
1
0
1
1
levels
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt priority
level
Priority
order
High
Low
Table 1.11.4. Interrupt levels enabled according
IPL
0
0
0
1
1
1
1
0
2
IPL
IPL
0
0
1
0
0
1
1
1
1
IPL
0
1
0
0
1
0
1
1
0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
to the contents of the IPL
Interrupt levels 1 and above are enabled
All maskable interrupts are disabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
Enabled interrupt priority levels
M16C / 62A Group
Mitsubishi microcomputers