M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 144

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UART2 Special Mode Register 2
Table 1.16.11. Functions changed by I
Table 1.16.12. Timing characteristics of detecting the start condition and the stop condition (Note1)
Note 1 : When the start/stop condition control bit SHTC is “1” .
Note 2 : “Cycles” is in terms of the input oscillation frequency f(X
1
2
3
4
5
3 to 6 cycles < duration for setting-up (Note2)
3 to 6 cycles < duration for holding (Note2)
Bit 0 of the UART2 special mode register 2 (address 0376
1.16.11 shows the types of control to be changed by I
is set to “1”. Table 1.16.12 shows the timing characteristics of detecting the start condition and the stop
condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to “1” in I
mode.
Factor of interrupt number 15
Timing for transferring data from the
UART2 reception shift register to the
reception buffer.
Factor of interrupt number 16
DMA1 factor at the time when 1 1 0 1
is assigned to the DMA request
factor selection bits
Timing for generating a UART2
reception/ACK interrupt request
(Start condition)
(Stop condition)
SDA
SDA
SCL
Function
Duration for
No acknowledgment detection (NACK) UART2 transmission (the rising edge
Acknowledgment detection (ACK)
Acknowledgment detection (ACK)
The rising edge of the final bit of the
reception clock
The rising edge of the final bit of the
reception clock
setting up
2
C mode select bit 2
IICM2 = 0
Duration for
2
C mode select bit 2 when the I
holding
16
) is used as the I
IN
) of the main clock.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 reception (the falling edge
of the final bit of the clock)
The falling edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
of the final bit of the clock)
UART2 reception (the falling edge of
the final bit of the clock)
2
C mode select bit 2. Table
IICM2 = 1
M16C / 62A Group
2
Mitsubishi microcomputers
C mode select bit
2
C
141