M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 135

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Clock asynchronous serial I/O (UART) mode
132
Table 1.16.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface)
Note 1: ‘n’ denotes the value 00
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
(3) Clock-asynchronous serial I/O mode (used for the SIM interface)
Transfer data format
Transfer clock
Transmission / reception control
Other settings
Transmission start condition • To start transmission, the following requirements must be met:
Reception start condition
Interrupt request
generation timing
Error detection
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table
1.16.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface).
that the UART2 receive interrupt request bit is not set to “1”.
Item
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 0378
• One stop bit (bit 4 of address 0378
• With the direct format chosen
• With the inverse format chosen
• With the internal clock chosen (bit 3 of address 0378
• Disable the CTS and RTS function (bit 4 of address 037C
• The sleep mode select function is not available for UART2
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D
• To start reception, the following requirements must be met:
• When transmitting
• When receiving
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
(Do not set external clock)
Set parity to “even” (bit 5 and bit 6 of address 0378
Set data logic to “direct” (bit 6 of address 037D
Set transfer format to LSB (bit 7 of address 037C
Set parity to “odd” (bit 5 and bit 6 of address 0378
Set data logic to “inverse” (bit 6 of address 037D
Set transfer format to MSB (bit 7 of address 037C
- Transmit enable bit (bit 0 of address 037D
- Transmit buffer empty flag (bit 1 of address 037D
- Reception enable bit (bit 2 of address 037D
- Detection of a start bit
When data transmission from the UART2 transmit register is completed
(bit 4 of address 037D
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
- On the reception side, an “L” level is output from the T
- On the transmission side, a parity error is detected by the level of input to
signal output function (bit 7 of address 037D
16
the R
to FF
X
D
16
2
_______
pin when a transmission interrupt occurs
that is set to the UART2 bit rate generator.
_______
16
= “1”)
Specification
16
= “0”)
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
= “1”) when a parity error is detected
= “0”) : fi / 16 (n + 1) (Note 1) : fi=f
16
16
16
16
) = “1”
16
) = “1”
X
16
= “0” and “1” respectively)
16
D
= “0”).
16
= “1” and “1” respectively)
2
= “1”)
= “0”).
16
pin by use of the parity error
= “1”)
) = “0”
16
M16C / 62A Group
Mitsubishi microcomputers
= “1”)
16
= “101
16
1
, f
= “1”)
8
2
, f
”)
32