M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 50

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
(2) Peripheral I/O interrupts
• Reset
• NMI interrupt
• DBC interrupt
• Watchdog timer interrupt
• Single-step interrupt
• Address match interrupt
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
• DMA0 interrupt, DMA1 interrupt
• Key-input interrupt
• A-D conversion interrupt
• UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt
• UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt
• Timer A0 interrupt through timer A4 interrupt
• Timer B0 interrupt through timer B5 interrupt
• INT0 interrupt through INT5 interrupt
Special interrupts are non-maskable interrupts.
Reset occurs if an “L” is input to the RESET pin.
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An NMI interrupt occurs if an “L” is input to the NMI pin.
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This interrupt is exclusively for the debugger, do not use it in other circumstances.
Generated by the watchdog timer.
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs.
This is an interrupt that the serial I/O bus collision detection generates.
These are interrupts that DMA generates.
A key-input interrupt occurs if an “L” is input to the KI pin.
This is an interrupt that the A-D converter generates.
These are interrupts that the serial I/O transmission generates.
These are interrupts that the serial I/O reception generates.
These are interrupts that timer A generates
These are interrupts that timer B generates.
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An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C / 62A Group
Mitsubishi microcomputers
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