M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 44

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Status Transition of BCLK
Status Transition of BCLK
Table 1.10.4. Operating modes dictated by settings of system clock control registers 0 and 1
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.10.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
0006
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
(2) Division by 4 mode
(3) Division by 8 mode
(4) Division by 16 mode
(5) No-division mode
(6) Low-speed mode
(7) Low power dissipation mode
Note : Before the count source for BCLK can be changed from X
Invalid
Invalid
Invalid
CM17
The main clock is divided by 2 to obtain the BCLK.
The main clock is divided by 4 to obtain the BCLK.
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
The main clock is divided by 16 to obtain the BCLK.
The main clock is divided by 1 to obtain the BCLK.
f
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
f
C
C
0
1
1
0
is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
is the BCLK and the main clock is stopped.
16
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
Invalid
Invalid
Invalid
CM16
1
0
1
0
CM07
0
0
0
0
0
1
1
Invalid
Invalid
CM06
0
0
1
0
0
CM05
0
0
0
0
0
0
1
Invalid
Invalid
Invalid
Invalid
Invalid
CM04
IN
1
1
to X
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CIN
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power dissipation mode
or vice versa, the clock to which
Operating mode of BCLK
M16C / 62A Group
Mitsubishi microcomputers
41