M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 68

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Watchdog Timer
Watchdog Timer
With X
Watchdog timer period =
With X
Watchdog timer period =
Figure 1.12.1. Block diagram of watchdog timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system.The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt
is generated when an underflow occurs in the watchdog timer. When X
the watchdog timer control register (address 000F
When X
timer control register (address 000F
below. The watchdog timer's period is, however, subject to an error due to the prescaler.
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 32.8 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E
watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or
state are released.
Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timer-
related registers.
Write to the watchdog timer
start register
(address 000E
IN
CIN
RESET
CIN
chosen for BCLK
HOLD
BCLK
chosen for BCLK
is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog
16
)
prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
prescaler dividing ratio (2) X watchdog timer count (32768)
Prescaler
16
1/128
1/16
1/2
). Thus the watchdog timer's period can be calculated as given
“CM07 = 0”
“WDC7 = 1”
“CM07 = 0”
“WDC7 = 0”
“CM07 = 1”
16
) selects the prescaler division ratio (by 16 or by 128).
BCLK
16
). In stop mode, wait mode and hold state, the
BCLK
Watchdog timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
IN
Set to
“7FFF
is selected for the BCLK bit 7 of
16
”
M16C / 62A Group
Mitsubishi microcomputers
Watchdog timer
interrupt request
16
) and when
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