M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 224

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CPU Rewrite Mode (Flash Memory Version)
Figure 1.26.2. CPU rewrite mode set/reset flowchart
Figure 1.26.3. Shifting to the low speed mode flowchart
Note 1: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bits (bit 6
Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed.
Note 1: For flash memory power supply-OFF bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
Note 2: Before the count source for BCLK can be changed from X
(Subsequent operations are executed by control
(Subsequent operations are executed by control
Jump to transferred control program in RAM
Transfer the program to be executed in the
Jump to transferred control program in RAM
low speed mode, to the internal RAM.
Single-chip mode, memory expansion
Set processor mode register (Note 1)
at address 0006
6.25 MHz or less when wait bit (bit 7 at address 0005
12.5 MHz or less when wait bit (bit 7 at address 0005
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of
an area other than the internal flash memory. Also only when NMI pin is “H” level.
execute a read array command or reset the flash memory.
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.
the count source is going to be switched must be oscillating stably.
Transfer CPU rewrite mode control
program to internal RAM
program in this RAM)
Program in ROM
program in this RAM)
mode, or boot mode
Program in ROM
Start
Start
16
*1
*1
and bits 6 and 7 at address 0007
16
Set flash memory power supply-OFF bit to “1”
(by writing “0” and then “1” in succession)(Note 1)
X
16
16
):
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
IN
Set flash memory power supply-OFF bit to “0”
Wait time until the internal circuit stabilizes
(Set NOP instruction about twice)
) = “0” (without internal access wait state)
) = “1” (with internal access wait state)
Switch the count source of BCLK.
X
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)(Note 2)
IN
(Boot mode only)
Write “0” to user ROM area select bit (Note 4)
oscillating
Switch the count source of BCLK (Note 2)
IN
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Write “0” to CPU rewrite mode select bit
to X
stop. (Note 2)
(Boot mode only)
Set user ROM area select bit to “1”
CIN
Process of low speed mode
Program in RAM
or vice versa, the clock to which
Program in RAM
Wait until the X
End
*1
End
*1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
IN
has stabilized
M16C / 62A Group
Mitsubishi microcomputers
221