AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 128

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

19.4
19.4.1
19.4.2
19.4.3
128
Arbitration
AT91SAM9261 Preliminary
Round-Robin Arbitration Without Default Master
Round-Robin Arbitration With Last Access Master
Round-Robin Arbitration With Fixed Default Master
The Bus Matrix provides an arbitration function that reduces latency when conflicting cases
occur, i.e., when two or more masters try to access the same slave at the same time. The Bus
Matrix arbitration mechanism uses slightly modified round-robin algorithms that grant the bus for
the first access to a certain master depending on parameters located in the slave’s Slave Con-
figuration Register.
There are three round-robin algorithm types:
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch
requests from different masters to the same slave in a pure round-robin manner. At the end of
the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency cycle for the first access. Arbitration without default master
can be used for masters that p23-Mar-09erform significant bursts.
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to
remove one latency cycle for the last master that accessed the slave. In fact, at the end of the
current transfer, if no other master request is pending, the slave remains connected to the last
master that performs the access. Other non-privileged masters still obtain one latency cycle if
they want to access the same slave. This technique can be used for masters that perform mainly
single accesses.
This is a biased round-robin algorithm. It allows the Bus Matrix arbiters to remove one latency
cycle for the fixed master of a slave. At the end of the current access, the slave remains con-
nected to its fixed default master. Any request attempted by this fixed default master does not
cause any latency, whereas other non-privileged masters still obtain one latency cycle. This
technique can be used for masters that perform mainly single accesses.
• Round-Robin arbitration without default master
• Round-Robin arbitration with last access master
• Round-Robin arbitration with fixed default master
6062M–ATARM–23-Mar-09