AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 740
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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ii
AT91SAM9261 Preliminary
10 Peripherals ............................................................................................. 28
11 ARM926EJ-S Processor Description ................................................... 39
12 AT91SAM9261 Debug and Test ............................................................ 57
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
12.1
12.2
Clock Generator ..............................................................................................24
Power Management Controller ........................................................................25
Periodic Interval Timer .....................................................................................25
Watchdog Timer ..............................................................................................25
Real-time Timer ...............................................................................................25
Advanced Interrupt Controller ..........................................................................26
Debug Unit .......................................................................................................26
PIO Controllers ................................................................................................27
User Interface ..................................................................................................28
Peripheral Identifiers ........................................................................................28
Peripheral Multiplexing on PIO Lines ..............................................................29
External Bus Interface .....................................................................................34
Static Memory Controller .................................................................................35
SDRAM Controller ...........................................................................................35
Serial Peripheral Interface ...............................................................................36
Two-wire Interface ...........................................................................................36
USART ............................................................................................................36
Synchronous Serial Controller .........................................................................37
Timer Counter ..................................................................................................37
Multimedia Card Interface ...............................................................................37
USB .................................................................................................................38
LCD Controller .................................................................................................38
Overview ..........................................................................................................39
Block Diagram .................................................................................................40
ARM9EJ-S Processor ......................................................................................40
CP15 Coprocessor ..........................................................................................48
Memory Management Unit (MMU) ..................................................................51
Caches and Write Buffer .................................................................................52
Tightly-Coupled Memory Interface ..................................................................54
Bus Interface Unit ............................................................................................55
Overview ..........................................................................................................57
Block Diagram .................................................................................................57
6062M–ATARM–23-Mar-09
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