AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 62

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12.5.5.2
Three-state Sequencer
Address Comparator
62
AT91SAM9261 Preliminary
Implementation Details
The trace packet information (address, data) is associated with the processor state indicated by
TPS. Some processor states have no additional data associated with the Trace Packet Port (i.e.,
failed condition code of an instruction). The packet is 8 bits wide, and up to two packets can be
output per cycle.
Figure 12-4. ETM9 Block
This section gives an overview of the Embedded Trace resources.
The sequencer has three possible next states (one dedicated to itself and two others) and can
change on every clock cycle. The state transition is controlled with internal events. If the user
needs multiple-stage trigger schemes, the trigger event is based on a sequencer state.
In single mode, address comparators compare either the instruction address or the data address
against the user-programmed address.
In range mode, the address comparators are arranged in pairs to form a virtual address range
resource.
Details of the address comparator programming are:
• TSYNC - the synchronization signal (Indicates the start of a branch sequence on the trace
• TCLK - the Trace Port clock, half-rate of the ARM926EJ-S processor clock.
• TPS0 to TPS2 - indicate the processor state at each trace clock edge.
• TPK0 to TPK15 - the Trace Packet data value.
• The first comparator is programmed with the range start address.
• The second comparator is programmed with the range end address.
packet port.)
ARM926EJ-S
Bus Tracker
Controller
TAP
Scan Chain 6
Trigger, Sequencer, Counters
Control
Trace
Trace Enable, View Data
FIFO
ETM9
TPS-TPS0
TPK15-TPK0
TSYNC
6062M–ATARM–23-Mar-09