AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 742

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AT91SAM9261-CJ-999

Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM9261-CJ-999

Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9261-CJ-999
Manufacturer:
Atmel
Quantity:
10 000
iv
AT91SAM9261 Preliminary
18 General Purpose Backup Register (GPBR) ....................................... 125
19 AT91SAM9261 Bus Matrix ................................................................... 127
20 External Bus Interface (EBI) ................................................................ 135
21 Static Memory Controller (SMC) ......................................................... 159
17.4
17.5
17.6
18.1
18.2
19.1
19.2
19.3
19.4
19.5
20.1
20.2
20.3
20.4
20.5
20.6
20.7
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
21.12
21.13
21.14
Product Dependencies ..................................................................................119
Functional Description ...................................................................................119
Shutdown Controller (SHDWC) User Interface .............................................121
Overview ........................................................................................................125
General Purpose Backup Registers (GPBR) User Interface ........................125
Overview ........................................................................................................127
Memory Mapping ...........................................................................................127
Special Bus Granting Techniques .................................................................127
Arbitration ......................................................................................................128
Bus Matrix (MATRIX) User Interface .............................................................129
Overview ........................................................................................................135
Block Diagram ...............................................................................................136
I/O Lines Description .....................................................................................137
Application Example ......................................................................................138
Product Dependencies ..................................................................................141
Functional Description ...................................................................................142
Implementation Examples .............................................................................150
Overview ........................................................................................................159
I/O Lines Description .....................................................................................159
Multiplexed Signals ........................................................................................159
Application Example ......................................................................................160
Product Dependencies ..................................................................................160
External Memory Mapping .............................................................................161
Connection to External Devices ....................................................................161
Standard Read and Write Protocols ..............................................................166
Automatic Wait States ...................................................................................174
Data Float Wait States ...................................................................................179
External Wait .................................................................................................183
Slow Clock Mode ...........................................................................................189
Asynchronous Page Mode ............................................................................192
Static Memory Controller (SMC) User Interface ............................................195
6062M–ATARM–23-Mar-09

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