AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 627

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Figure 38-5. TFT Panel Timing (Line Expanded View), CLKMOD=1
6062M–ATARM–23-Mar-09
LCDHSYNC
LCDDOTCK
LCDVSYNC
LCDDEN
LCDD
--------------------------- -
f
LCDVSYNC
VHDLY+1
1
=
Usually the LCD_FRM rate is about 70 Hz to 75 Hz. It is given by the following equation:
where:
In STN Mode:
In monochrome mode, Horizontal_display_size is equal to the number of horizontal pixels. The
number_data_lines is equal to the number of bits of the interface in single scan mode;
number_data_lines is equal to half the bits of the interface in dual scan mode.
In color mode, Horizontal_display_size equals three times the number of horizontal pixels.
In TFT Mode:
The frame rate equation is used first without considering the clock periods added at the end
beginning or at the end of each line to determine, approximately, the LCDDOTCK rate:
With this value, the CLKVAL is fixed, as well as the corresponding LCDDOTCK rate.
Then select VHDLY, HPW and HBP according to the type of LCD used and
page
Finally, the frame rate is adjusted to 70 Hz - 75 Hz with the HFP value:
• HOZVAL determines de number of LCDDOTCK cycles per line
• LINEVAL determines the number of LCDHSYNC cycles per frame, according to the
⎛
⎝
HPW+1
VHDLY
-------------------------------------------------------------------------------------------------------------------- -
expressions shown below:
624.
+
HBP+1
HPW
f
HOZVAL
LINEVAL
HOZVAL
LINEVAL
lcd_pclk
+
f
LCDDOTCK
HBP
1 PCLK
=
=
=
=
=
(
HOZVAL
+
Horizontal_display_size 1
Horizontal_display_size
-------------------------------------------------------------- - 1
Vertical_display_size 1
Vertical_display_size 1
HOZVAL
Line Period
Number_data_lines
1/2 PCLK 1/2 PCLK
+
5
+
)
HFP
×
(
f
lcd_vsync
AT91SAM9261 Preliminary
+
5
⎞ VBP
⎠
HOZVAL+1
(
–
–
–
–
×
(
+
LINEVAL
LINEVAL
+
+
1
VFP
)
)
+
1
)
“Equation 1” on
HFP+2
627