AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 724

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

724
Doc. Rev.
6062K
AT91SAM9261 Preliminary
Date
27-Aug-08 Comments (Continued)
RSTC:
Figure 14-4 ”Genera Reset
Section 14.3.4.1 ”General
Section 14.3.3 ”BMS Sampling”
Section 14.3.4.4 ”Software
purposes.
SHDWC:
Table 17-2, “Register Mapping”
SHDW_MR reset changed to 0x0000_0303.
SHDW_SR offset value is 0x08.
SDRAMC:
Section 22.6.1 ”SDRAMC Mode
Section 22.6.3 ”SDRAMC Configuration Register”
SMC:
Section 21.8.5 ”Coding Timing
updated in
Section 21.9.3.1 ”User
Chip Select added
SPI:
Section 30.6.4 ”SPI Slave
SPI_RDR.
Section 30.7.9 ”SPI Chip Select
referenced in the BITS bit field description and
SSC:
Section 33.8.3 ”SSC Receive Clock Mode
16.
TC:
Section 34.6 ”Timer Counter (TC) User
Table 34-4, “Register Mapping”
From
register names updated with indexed offset reference. Functional value of WAVE is given, when
relevant, in Register Name or Access.
Section 34.6.2 ”TC Block Mode
Section 34.6.4 ”TC Channel Mode Register: Capture
Section 34.6.5 ”TC Channel Mode Register: Waveform
TWI:
Section 31. ”Two Wire Interface
Section 34.6.3 ”TC Channel Control Register”
Table
21-4.
Procedure”, added instructions regarding configuration parameters of SMC
Reset”, extensive update to this section.
Mode”, corrected information on OVRES (SPI_SR) and data read in
Reset”, PERRST must be used with PROCRST, except for deug
State”, updated
Parameters”, “Effective Value” column under “Permitted Range”
as a result of indexed register scheme.
Register”, typo corrected in bit fields 2 and 3.
and
Register”, note pertaining to BITS field added. This note is
(TWI)”, extensive update to this section.
Register”, changed MODE bit descriptions .
Figure 14-3 ”BMS Sampling”
Interface”, previous Register Mapping tables consolidated in
Register”, Corrected name to STTDLY in bit fields 23 to
Section 30.6.4 ”SPI Slave
Changed bit description for
to
Mode”, bit field 15 updated.
Section 34.6.13 ”TC Interrupt Mask
Mode”, bit field 15 updated.
added to datasheet
Mode”.
“CAS: CAS
Register”,
Latency”.
6062M–ATARM–23-Mar-09
Change
Request
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