AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 736

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

736
Doc. Rev.
6062B
AT91SAM9261 Preliminary
Date
14-Oct-05
Comments
Changed SPI pin names in
Table 3-1, “Signal Description by Peripheral,” on page
Controller A,” on page
Table 10-3, “Multiplexing on PIO Controller C,” on page
Corrected EBI/Compact Flash interface description with updated A22 pin functionality in
Figure 2-1, “AT91SAM9261 Block Diagram,” on page
External Bus Interface,” on page 131
page
Changed value of programmable pull-up resistor in
Lines” on page
Bus Matrix: Corrected reset values of Slave Configuration Registers 0, 1 and 2 in
1, “Register Mapping,” on page
Bus Matrix: Updated bit information in
on page
SMC: Corrected reset values of SMC_SETUP, SMC_CYCLE and SMC_MODE in
Table 21-9, “SMC Register Mapping,” on page
SDRAMC: Removed Hardware Interface section from
on page
SDRAMC: Updated
PMC: Updated
PMC: Updated
Figure 25-6, “Change PLLB Programming,” on page
PMC: Added important note on programming Bit 29 of CKGR_PLLAR in
”Programming Sequence” on page 229
A Register” on page
AIC: Added information on external interrupt sources for bit SRCTYPE in
”AIC Source Mode Register” on page
DBGU: Updated bit description for SRAMSIZ in
Register” on page
PIO: Removed reference to resistor value in
page
SPI: References to MCK/32 removed throughout.
page 338
SPI:
SPI_TNCR location defined.
SPI:
text added.
SPI:
changed
MCI: Corrected pin names in
page
UHP: Added information on memory access errors in
Section 29.7.5 ”SPI Status Register” on page 356
Section 29.7.4 ”SPI Transmit Data Register” on page
Section 29.7.2 ”SPI Mode Register” on page
139.
331.
498.
134.
188.
and
Figure 29-5, “Master Mode Block Diagram,” on page 343
Section 25.8 ”Programming Sequence” on page
Figure 25-5, “Change PLLA Programming,” on page 235
12.
300.
Figure 22-2, “SDRAM Device Initialization Sequence,” on page
245.
30,
Table 10-2, “Multiplexing on PIO Controller B,” on page 31
Figure 2-1, “AT91SAM9261 Block Diagram,” on page
Figure 34-4, “MMC Bus Connections (One Slot),” on
129.
and
267.
Section 19.5.5 “USB Pad Pull-up Control Register”
and in
Table 20-6, “CFCE1 and CFCE2 Truth Table,” on
Section 28.4.1 ”Pull-up Resistor Control” on
Section 25.10.9 ”PMC Clock Generator PLL
181.
Section 27.5.10 ”Debug Unit Chip ID
Figure 29-1, “Block Diagram,” on
352,
Section 6.4 ”PIO Controller A, B and C
235.
“USB Host Port (UHP)”
4,
Section 22.4 ”Application Example”
5,
PCSDEC: Chip Select Decode on
SPI_RCR, SPI_RNCR, SPI_TCR,
32.
Figure 20-1, “Organization of the
Table 10-1, “Multiplexing on PIO
355,
LASTXFER: Last Transfer
229.
changed.
and added
Section 25.8
Section 26.8.3
on
page
Table 19-
4,
191.
6062M–ATARM–23-Mar-09
and
522.
Change
Request
Reference
05-398
05-481
05-496
05-498
05-486
05-499
05-468
05-479
05-393
05-198
05-239
05-269
05-306
05-497
05-484
04-183
05-434
05-476
05-308
05-240