AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 732

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

732
Doc. Rev.
6062D
AT91SAM9261 Preliminary
Date
14-Apr-06
Comments
Updated information on JTAGSEL in
page 5
Reformatted
Memory Mapping,” on page 16
Inserted new
Removed information on Timer Counter clock assignments in
Counter” on page
In section Debug and Test, added
RSTC: In
startup counter.
RTT: Added note to
asynchronism between SCLK and MCK.
SHDWC: In
account only 2 slow clock cycles after the write of SHDW_CR.”
Bus Matrix: Removed bits RCB4, RCB3 and RCB2 from MATRIX_MCFG in
“Bus Matrix Master Configuration Register” on page
EBI: Added
PMC: Updated OUTx bit descriptions in
Register” on page 270
page
PMC: Added note defining PIDx in
Register” on page
266
PMC: Updated document to with details on oscillator selection. Added bit OSCSEL to
Section 25.10.15 ”PMC Status Register” on page
PMC: Addition of PLL Charge Pump Current Register in
on page 262
AIC:
field to AIC_SVR register changed to AIC_SMR register.
AIC:
27-2
AIC: Naming convention for AIC_FVR register harmonized in
Mapping,” on page 290
DBGU: In
signal ice_reset to pad Power_on Reset. Also changed in bit description FNTRST in
Section 27.5.12 ”Debug Unit Force NTRST Register” on page
USART: MANE bit removed from
page
and
Section 27.7.3.1 “Priority Controller” on page
Section 27.8 “Advanced Interrupt Controller (AIC) User Interface” on page
added note in reference to PID2...PID31 bit fields.
271.
432.
and in
Section 25.10.6 ”PMC Peripheral Clock Status Register” on page
Section 14.3.1 ”Reset Controller Overview” on page
Figure 27-1, “Debug Unit Functional Block Diagram,” on page
Section 20.7 “Implementation Examples” on page
Section 18.5 ”Functional Description”
Section 8. ”Memories” on page
and
Section 8.1.2 ”Boot Strategies” on page 20
Section 6.1 ”JTAG Port Pins” on page
Section 25.10.17 ”PLL Charge Pump Current Register” on page
37.
266,
Section 15.3 ”Functional Description”
and
Section 25.10.5 ”PMC Peripheral Clock Disable Register” on page
and
Section 25.10.10 ”PMC Clock Generator PLL B Register” on
“Fast Forcing” on page
to show full product memory mapping.
Section 31.7.3 ”USART Interrupt Enable Register” on
Section 12.5.3 “JTAG Signal Description” on page
Section 25.10.4 ”PMC Peripheral Clock Enable
Section 3-1 ”Signal Description by Peripheral” on
Section 25.10.9 ”PMC Clock Generator PLL A
16. Inserted new
275.
283, incorrect reference of SRCTYPE
added “The shutdown is taken into
287.
130.
11.
Table 25-3, “Register Mapping,”
to replace Boot ROM section.
giving information on
Table 27-2, “Register
Section 10.11 ”Timer
Figure 8-1, “AT91SAM9261
95, added information on
150.
325.
304, changed
267.
Section 19.5.1
290,
277.
Table
6062M–ATARM–23-Mar-09
60.
Change
Request
Reference
2946
2475
2480
2474
2557
3005
2522
2549
2731
2467
2468
2558
2568
2512
2548
2524
2747