AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 710

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

42.3.6.3
42.3.6.4
42.3.7
42.3.7.1
42.3.8
42.3.8.1
710
AT91SAM9261 Preliminary
NTRST
Reset Controller (RSTC)
MCI: STREAM command not supported
MCI: STOP during a WRITE_MULTIPLE_BLOCK command
NTRST: Device does not boot correctly due to power-up sequencing issue
RSTC: Reset During SDRAM Accesses
A STOP command must be sent with a software timeout.
The STREAM READ/WRITE commands are not supported by the MCI.
None.
The WRITE_MULTIPLE_BLOCK with a transfer size (PDC) not a multiple of the block length is
not stopped by the STOP command.
Choose an appropriate size for the block length.
The NTRST signal is powered by VDDIOP power supply (3.3V) and the ARM processor is pow-
ered by VDDCORE power supply (1.2V).
During the power-up sequence, if VDDIOP power supply is not established whereas the
VDDCORE Power On Reset output is released, the NTRST signal is not correctly asserted. This
leads to a bad reset of the Embedded Trace Macrocell (ETM9). The ARM processor then enters
debug state and the device does not boot correctly.
When a User Reset occurs during SDRAM read access, the SDRAM clock is turned off while
data are ready to be read on the data bus. The SDRAM maintains the data until the clock
restarts.
If the user Reset is programmed to assert a general reset, the data maintained by the SDRAM
leads to a data bus conflict and adversely affects the boot memories connected on the EBI:
In the interrupt routine, Power Down SDRAM properly and perform Peripheral and Processor
Reset with software in assembler.
Example with libV3.
1. Connect NTRST pin to NRST pin to ensure that a correct powering sequence takes
2. Connect NTRST to GND if no debug capabilities are required.
• NAND Flash boot functionality, if the system boots out of internal ROM.
• NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
1. Avoid User Reset to generate a system reset.
2. Trap the User Reset with an interrupt.
• The main code:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
//user reset interrupt setting
place in all cases.
6062M–ATARM–23-Mar-09