AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 260
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AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
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Manufacturer
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25.9.9
Name:
Address:
Access Type:Read-write
Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider A
• PLLACOUNT: PLL A Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLL A Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MULA: PLL A Multiplier
0 = The PLL A is deactivated.
1 up to 2047 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1.
6062M–ATARM–23-Mar-09
DIVA
0
1
2 - 255
31
23
15
–
7
PMC Clock Generator PLL A Register
OUTA
CKGR_PLLAR
0xFFFFFC28
30
22
14
–
6
29
21
13
1
5
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the Main Clock divided by DIVA.
28
20
12
–
4
MULA
DIVA
27
19
11
–
3
PLLACOUNT
AT91SAM9261 Preliminary
26
18
10
2
MULA
25
17
9
1
24
16
8
0
260
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