AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 60

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12.5
12.5.1
12.5.2
12.5.3
60
Functional Description
AT91SAM9261 Preliminary
Test Pin
Embedded In-circuit Emulator
JTAG Signal Description
Table 12-1.
One dedicated pin, TST, is used to define the device operating mode. The user must make sure
that this pin is tied at low level to ensure normal operating conditions. Other values associated
with this pin are reserved for manufacturing test.
The ARM9EJ-S EmbeddedICE-RT
host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core
embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through
an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core
without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can
be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers.
This data can be serially shifted out without affecting the rest of the system.
There are two scan chains inside the ARM9EJ-S processor which support testing, debugging,
and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG
port.
EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the EmbeddedICE-RT, see the ARM document ARM9EJ-S Technical Ref-
erence Manual (DDI 0222A).
TMS is the Test Mode Select input which controls the transitions of the test interface state
machine.
TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan
Register, Instruction Register, or other data registers).
TDO is the Test Data Output line which is used to serially output the data from the JTAG regis-
ters to the equipment controlling the test. It carries the sampled values from the boundary scan
chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit.
NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM
cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a
Power On Reset output. It is asserted on power on. If necessary, the user can also reset the
debug logic with the NTRST pin assertion during 2.5 MCK periods.
TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment
controlling the test and not by the tested device. It can be pulsed at any frequency. Note the
maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45
kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock.
DRXD
DTXD
Debug and Test Pin List
Debug Receive Data
Debug Transmit Data
™
is supported via the ICE/JTAG port. It is connected to a
Debug Unit
Output
Input
6062M–ATARM–23-Mar-09