AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 624

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

38.5.2.9
624
AT91SAM9261 Preliminary
Equation 1
Table 38-10. Minimum LCDDOTCK Period in LCDC Core Clock Cycles
The LCDDEN signal indicates valid data in the LCD Interface.
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to
cause the line to be displayed on the panel.
The following timing parameters can be configured:
There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by
the initial latency of the datapath. The total delay in LCDC clock cycles must be higher than or
equal to the latency column in
formula:
where:
DISTYPE
TFT
STN Mono
STN Mono
STN Mono
STN Mono
STN Color
STN Color
STN Color
STN Color
• Vertical to Horizontal Delay (VHDLY): The delay between begin_of_line and the generation of
• Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of
• Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first
• Horizontal Front Porch (HFP): The delay between end of valid data and the end of the line is
• VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers
• PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles
• DPATH_LATENCY is the datapath latency of the configuration, given in
LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to
(VHDLY+1) LCDDOTCK cycles.
LCDTIM2 register. The width is equal to (HPW + 1) LCDDOTCK cycles.
LCDDOTCK rising edge with valid data at the LCD Interface is configurable in the HBP field
of the LCDTIM2 register. The delay is equal to (HBP+1) LCDDOTCK cycles.
configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+2)
LCDDOTCK cycles.
618
(
VHDLY
+
HPW
SCAN
Single
Single
Dual
Dual
Single
Single
Dual
Dual
Configuration
+
Table 38-2 on page
HBP
+
3
)
×
PCLK_PERIOD
IFWIDTH
4
8
8
16
4
8
8
16
618. This limitation is given by the following
≥
DPATH_LATENCY
LCDDOTCK Period
1
4
8
8
16
2
2
4
6
Table 38-2 on page
6062M–ATARM–23-Mar-09