AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 214

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

22.6.1
Register
Address:
Access Type:Read-write
Reset Value: 0x00000000
• MODE: SDRAMC Command Mode
This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
6062M–ATARM–23-Mar-09
0
0
0
0
1
1
1
MODE
31
23
15
–
–
–
7
–
0
0
1
1
0
0
1
SDRAMC Mode Register
SDRAMC_MR
0xFFFFEA00
0
1
0
1
0
1
0
Description
Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed
by a write to the SDRAM.
The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To
activate this mode, command must be followed by a write to the SDRAM.
The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed
regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
The SDRAM Controller issues an “Auto-Refresh” Command when the SDRAM device is accessed regardles of
the cycle. Previously, an “All Banks Precharge” command must be issued. To activate this mode, command must
be followed by a write to the SDRAM.
The SDRAM Controller issues an “Extended Load Mode Register” command when the SDRAM device is
accessed regardless of the cycle. To activate this mode, the “Extended Load Mode Register” command must be
followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-
power SDRAM devices use the bank 1.
Deep power-down mode. Enters deep power-down mode.
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
AT91SAM9261 Preliminary
26
18
10
–
–
–
2
MODE
25
17
–
–
9
–
1
24
16
–
–
8
–
0
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