AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 725

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

6062M–ATARM–23-Mar-09
Doc. Rev.
6062K
Date
27-Aug-08 Comments (Continued)
UDP:
Table 37-2, “USB Communication Flow”
“Supported Endpoint Size” column.
Control endpoints are not effected by the
UDP_CSR register.
Updated “write 1 =....” in
Updated “write 0 =....” in
Section 37.6.10 ”UDP Endpoint Control and Status
regarding USB clock and system clock cycle.
by Master Clock domain, UDPCK specified as 48 MHz clock used by 12 MHz domain, in peripheral
clock requirements.
Table 37-4, “Register
footnote added to UDP_ISR reset.
Section 37.6.6 ”UDP Interrupt Mask
Table 37-4, “Register
Table 37-1, “USB Endpoint
Section 37.5.2.9 ”Transmit Data
Section 37.6.9 ”UDP Reset Endpoint
”TXPKTRDY: Transmit Packet
UHP:
Section 36.1
http://h18000.www1.hp.com/productinfo/development/openhci.html.
USART:
Section 32.5.1 ”I/O
hardware handshaking feature.
Section 32.6.2 ”Receiver and Transmitter
(RSTRX and RSTTX in US_CR register) updated by replacing 2nd sentence.
Section 32.6.3.1 ”Transmitter
Section 32.6.5 ”IrDA
Electrical Characteristics:
Section 39.8 ”EBI
extensive updates to these sections.
Section 39.7 Core Power Supply POR Characteristics removed, subsequent number has changed. 5795
Table 39-19, “SMC Write Signals with Hold Settings”
SMC
Table 39-20, “SMC Write Signals with No Hold Settings (NWE Controlled Only)”
SMC
Figure 39-2 ”USB Data Signal Rise and Fall
Mechanical Characteristics:
Table 40-1, “Soldering Information (Substrate Level),” on page
Revision History:
Doc. Rev., ”6062H”, Change Request Ref.,”4241”, removed : “PA30 - PA31 power supplies are
VDDIOM.”
Section 37.2 ”Block
23
40
: in “Min” columns, -1 removed from (NWE pulse length).
and SMC
”Overview”, Added hyperlink to Open HCI Rev 1.0 Specification.
34
Timings”,
: in “Min” columns, -1 removed from (NWE pulse length).
Lines”, added sentence on required use of internal pull up on TXD pertaining to
Diagram”, text under the block diagram updated: MCK specified as clock used
Mode”, updated with instructions to receive IrDA signals.
Mapping”, UDP_CSR, UDP_FDR updated with indexed register scheme,
Mapping”, Reset vaule for UDP_RST_EP is 0x000_0000
”RX_DATA_BK0: Receive Data Bank 0”
”TXPKTRDY: Transmit Packet Ready”
Description”, footnote added to Dual-Bank heading.
Section 39.9 ”SDRAMC
Operations”, last paragraph updated.
Ready”, description in UDP_CSRx, updated “Write :0 = .....“.
Cancellation”, added.
Register”, bitfield 12 defined as BIT12, cannot be masked.
Register”, added steps to clear endpoints.
changed the value in the cell on the “interrupt line of the
”EPEDS: Endpoint Enable Disable”
Control”, In the fourth paragraph, Software reset effects
Times”, R
Register”, update to code and added instructions
TImings”,
EWXT
AT91SAM9261 Preliminary
= 27 Ohms.
Section 39.10 ”Peripheral Timings”
690, updated.
bit field of UDP_CSR register.
bit field of UDP_CSR register.
bit field in the
Change
Request
Ref.
3476
4063
4099
4462/4487
4508
4802
5049
5150
4364
4285
4367
rfo
4912
5609
5527
5612
5822
5333
725