AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 29

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

10.3
10.3.1
10.3.1.1
10.3.1.2
10.3.1.3
10.3.1.4
6062M–ATARM–23-Mar-09
Peripheral Multiplexing on PIO Lines
Resource Multiplexing
LCD Controller
ETM
EBI
32-bit Data Bus
The AT91SAM9261 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O
lines of the peripheral set.
Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two
peripheral functions, A or B.
page 33
lers. The two columns “Function” and “Comments” have been inserted for the user’s own
comments; they may be used to track how pins are defined in an application.
Note that some output only peripheral functions might be duplicated within the tables.
The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device
is maintained in a static state as soon as the reset is released. As a result, the bit corresponding
to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this func-
tion and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel
without any limitation. Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the
chip select line 0 of the SPI1.
16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output
on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on
LCDD2, LCDD10 and LCDD18. Using the peripheral B does not prevent using the SSC0 and
the SPI1 lines.
Using the ETM prevents:
If not required, the NWAIT function (external wait request) can be deactivated by software,
allowing this pin to be used as a PIO.
Using a 32-bit Data Bus prevents:
• using the USART1 and USART2 control signals, in particular the SCK lines which are
• using the SSC1
• addressing a static memory of more than 8 Mbytes, which requires the A23 and A24 address
• using the chip select lines 1 to 3 of SPI0 and SPI1
required to use the USART as ISO7816 and the RTS and CTS to handle hardware
handshaking on the serial lines. In case the ETM and an ISO7816 connection are both
required, the USART0 has to be used as a Smart Card interface.
lines
define how the I/O lines of the peripherals A and B are multiplexed on the PIO Control-
Table 10-2 on page
AT91SAM9261 Preliminary
31,
Table 10-3 on page 32
and
Table 10-4 on
29