AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 401

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

31.9.5.6
Figure 31-29. Clock Synchronization in Write Mode
Notes:
401
TWI_RHR
TXCOMP
SVREAD
SCLWS
RXRDY
SVACC
TWCK
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
TWD
AT91SAM9261 Preliminary
SADR.
nism is finished.
Clock Synchronization in Write Mode
S
SADR
As soon as a START is detected
The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or
REPEATED_START condition was not detected, it is tied low until TWI_RHR is read.
Figure 31-29 on page 401
W
A
DATA0
CLOCK is tied low by the TWI as long as RHR is full
A
describes the clock synchronization in Read mode.
DATA1
DATA0 is not read in the RHR
SCL is stretched on the last bit of DATA1
Rd DATA0
A
Rd DATA1
DATA1
DATA2
NA
Rd DATA2
DATA2
6062M–ATARM–23-Mar-09
S
ADR