AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 370
AT91SAM9261-CJ-999
Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261-CJ-999.pdf
(749 pages)
Specifications of AT91SAM9261-CJ-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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30.7.5
Name:
Addresses: 0xFFFC8010 (0), 0xFFFCC010 (1)
Access Type: Read-only
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read
of SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR
• RXBUFF: RX Buffer Full
0 = SPI_RCR
1 = Both SPI_RCR
370
TXBUFE
31
23
15
–
–
–
7
AT91SAM9261 Preliminary
SPI Status Register
(1)
SPI_SR
or SPI_RNCR
RXBUFF
(1)
and SPI_RNCR
30
22
14
–
–
–
6
(1)
has a value other than 0.
ENDTX
29
21
13
(1)
–
–
–
5
have a value of 0.
ENDRX
28
20
12
–
–
–
4
OVRES
27
19
11
–
–
–
3
MODF
(1)
(1)
26
18
10
–
–
–
2
or SPI_RNCR
or SPI_TNCR
(1)
(1)
or SPI_RNCR
or SPI_TNCR
TXEMPTY
TDRE
(1)
(1)
25
17
–
–
9
1
.
.
(1)
(1)
6062M–ATARM–23-Mar-09
.
.
SPIENS
NSSR
RDRF
24
16
–
8
0
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