AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 708

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

42.3.3
42.3.3.1
42.3.3.2
42.3.4
42.3.4.1
42.3.5
42.3.5.1
42.3.5.2
708
AT91SAM9261 Preliminary
Boot ROM
Bus Matrix
LCD
Boot ROM: Temperature Range
Boot ROM: UDP Pad Pull-up Enable
Bus Matrix: Problem with locked transfers261
LCD: Screen shifting after a reset
LCD: Periodic bad pixels
The temperature range for the Boot ROM use is 0°C / 70°C.
Starting up the device outside this temperature range can lead to unpredictable behavior. If the
AT91SAM9261-based system may have to start up at temperatures below 0° C and above
70° C, it is recommended to boot out of an external memory connected on NCS0.
None.
When AT91SAM9261 boots on internal ROM (BMS = 1), the UDP pad pull-up is enabled by soft-
ware. This can lead to an enumeration error.
Disable UDP pad pull-up at the beginning of the boot program (ex: at91bootstrap).
Locked transfers are not correctly handled by the Bus Matrix and can lead to a system freeze
up. This does not concern ARM locked transfers.
Avoid other Bus Matrix masters locked transfers.
When a FIFO underflow occurs, a reset of the LCD DMA and FIFO pointers is necessary.
If only LCD DMA pointers are reset (FIFO pointers not reset), the displayed image is shifted.
Apply the following sequence to correctly reset LCD DMA and FIFO pointers:
Powering LCD off, then powering LCD on, resets the FIFO pointers.
Disabling DMA, then enabling DMA, resets the DMA pointers.
LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA per-
forms bursts to read memory. The LCD DMA bursts must not cross the 1-Kbyte AMBA
boundary.
• LCD power off
• DMA disable
• Wait for DMABUSY
• DMA reset
• LCD power on
• DMA enable.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6062M–ATARM–23-Mar-09