AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 709

no-image

AT91SAM9261-CJ-999

Manufacturer Part Number
AT91SAM9261-CJ-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM9261-CJ-999

Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
192K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9261-CJ-999
Manufacturer:
Atmel
Quantity:
10 000
42.3.5.3
42.3.6
42.3.6.1
42.3.6.2
6062M–ATARM–23-Mar-09
MCI
LCD: 24-bit Packed Mode
MCI: Busy signal of R1b responses is not taken in account
MCI: Data Timeout Error Flag
The LCD DMA burst size in 32-bit words is programmed by BRSTLN field in DMAFRMCFG
register.
The LCD DMA Base Address is programmed in DMABADDR1 register.
The LCD DMA Base Address must be programmed with a value aligned onto LCD DMA burst
size, e.g.:
BRSTLN = 15
For a 16-word burst, the LCD DMA Base Address must start on a 16-word offset: 0x0, 0x40,
0x80 or 0xc0.
BRSTLN = 3
For a 4-word burst, the LCD DMA Base Address offset must start on a 4-word offset: 0x0, 0x10,
..., 0xf0.
LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed
mode. A 32-bit word contains some bits of a pixel and some bits of the following. If LCD DMA
Base Address is not aligned with a pixel start, the colors will be modified.
Respect "LCD periodic bad pixels" erratum constrains lead to select the LCD DMA Base
Address regarding the LCD DMA burst size.
Problem Fix/Workaround
LCD DMA Base Address is to be set on a pixel start, every three 32-bit word.
The offset of the LCD DMA Base Address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or
0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8,
0xb4, 0xc0 ...)
e.g. regarding the bursts size:
1) BRSTLN = 3 implies the following LCD DMA Base Address offsets: 0x0, 0x30, 0x60, ...
2) BRSTLN = 15 implies the following LCD DMA Base Address offsets: 0x0 and 0xc0 only.
The busy status of the card during the response (R1b) is ignored for the commands CMD7,
CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56 a
conflict can occur on data line 0 if the MCI sends data to the card while the card is still busy.
The behavior is correct for CMD12 command (STOP_TRANSFER).
None
As the data timeout error flag cannot rise, the MCI is stalled indefinitely waiting for the data start
bit.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9261 Preliminary
709

Related parts for AT91SAM9261-CJ-999