AT91SAM9261-CJ-999 Atmel, AT91SAM9261-CJ-999 Datasheet - Page 712

• Manufacturer Part Number: AT91SAM9261-CJ-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261-CJ-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

42.3.9
42.3.9.1
42.3.9.2
42.3.9.3
42.3.10
42.3.10.1
712
AT91SAM9261 Preliminary
SDRAM Controller
Serial Peripheral Interface (SPI)
SDRAM: SDCLK Clock active after reset
SDRAM: JEDEC Standard Compatibility
SDRAM: Mobile SDRAM Device Initialization Constraint
SPI: Pulse Generation on SPCK
After a reset the SDRAM clock is always active leading in over consumption in the pad.
The following sequence allows to stop the SDRAM clock.
In the current configuration, SDCKE rises at the same time as SDCK, while exiting self-refresh
mode. To be fully compliant with the JEDEC standard, SDCK must be stable before the rising
edge of SDCKE. This is not the case in this product.
Use a fully JEDEC compliant SDRAM module.
Using Mobile SDRAM devices that need to have their DQMx level HIGH during the Mobile
SDRAM device intialization, may lead to data bus contention. Therefore, external memories on
the same EBI must not be accessed.
This does not apply to Mobile SDRAM devices whose DQMx level is “don’t care” during this
phase.
Mobile SDRAM initialization must be performed in internal SRAM.
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as
follows:
1. Set the bit LPCB to 01 (Self-refresh) in the SDRAMC Low Power Register.
2. Write 0 in the SDRAMC Mode Register and perform a dummy write in sdram to
;perform power down command
;perform proc_reset and periph_reset (in the ARM pipeline)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
complete.
– The Baudrate is odd and different from 1.
– The Polarity is set to 1.
– The Phase is set to 0 .
LDR r2, =AT91C_RSTC_RCR
LDR r3, =0xA5000005
STR r1, [r0]
STR r3, [r2]
END
6062M–ATARM–23-Mar-09