Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 10

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
DS0200-003
Chapter 19: Universal Serial Bus (USB) ...................................................................... 155
Chapter 20: General-Purpose Input/Output (GPIO) ............................................... 172
18.6 Error Detection................................................................................................................................... 148
18.7 SPI Interrupts ....................................................................................................................................... 148
18.8 SPI Baud Rate Generator (BRG)..................................................................................................... 149
18.9 SPI Registers (Base: SPI0→FFFEE00h, SPI1→FFFEF000h) ................................................................ 149
19.1 Buffer Descriptor Table..................................................................................................................... 155
19.2 Receive vs. Transmit ......................................................................................................................... 157
19.3 Buffer Descriptor Addressing........................................................................................................... 157
19.4 USB Transaction ................................................................................................................................. 157
19.5 Host Mode Operation ...................................................................................................................... 158
19.6 On-The-Go operation ...................................................................................................................... 159
19.7 External Configuration ..................................................................................................................... 161
19.8 Registers (Base → FFFBD000h)......................................................................................................... 162
20.1 GPIO Configuration .......................................................................................................................... 173
20.2 Multiplexed Pins................................................................................................................................. 174
18.6.1 Transmit Overrun.............................................................................................................148
18.6.2 Mode Fault (Multi-Master Collision) ..............................................................................148
18.6.3 Slave Mode Abort ..........................................................................................................148
18.6.4 Receive Overrun ............................................................................................................148
18.9.1 Offset 00h: SPI_DAT – SPI Data Register ........................................................................149
18.9.2 Offset 04h: SPI_CTL – SPI Control Register.....................................................................150
18.9.3 Offset 08h: SPI_STA – SPI Status Register .......................................................................151
18.9.4 Offset 0Ch: SPI_MOD – SPI Mode Register ...................................................................152
18.9.5 Offset 10h: SPI_DIAG – SPI Diagnostic State Register ..................................................152
18.9.6 Offset 14h: SPI_BRG – SPI Baud Rate Register ..............................................................153
18.9.7 Offset 18h: SPI_DMA – SPI DMA Register ......................................................................154
19.5.1 Discover a Connected Device.....................................................................................158
19.5.2 Perform a Control Transaction to Device ....................................................................158
19.5.3 Send a Full Speed Bulk Data to Target Device............................................................159
19.6.1 OTG Dual Role “B” Device Operation..........................................................................159
19.6.2 OTG Dual Role “A” Device Operation .........................................................................160
19.8.1 Offset 000h: USB_PER_ID – Peripheral ID Register.........................................................162
19.8.2 Offset 004h: USB_ID_COMP – Peripheral ID Compliment Register.............................163
19.8.3 Offset 008h: USB_REV – Peripheral Revision Register ...................................................163
19.8.4 Offset 00Ch: USB_ADD_INFO – Peripheral Additional Info Register ...........................163
19.8.5 Offset 010h: USB_OTG_ISTAT – OTG Interrupt Status Register......................................164
19.8.6 Offset 014h: USB_OTG_IEN – OTG Interrupt Control Register ......................................164
19.8.7 Offset 018h: USB_OTG_STAT – OTG Status Register ......................................................165
19.8.8 Offset 01Ch: USB_OTG_CTL – OTG Control Register....................................................165
19.8.9 Offset 080h: USB_ISTAT – Interrupt Status Register ........................................................166
19.8.10 Offset 084h: USB_IEN – Interrupt Enable Register .........................................................166
19.8.11 Offset 088h: USB_ESTAT – Error Interrupt Status Register ..............................................167
19.8.12 Offset 08Ch: USB_EEN – Error Interrupt Enable Register...............................................167
19.8.13 Offset 090h: USB_STAT – USB Status Register .................................................................168
19.8.14 Offset 094h: USB_CTRL – USB Control Register..............................................................168
19.8.15 Offset 098h: USB_ADDR – USB Address Register...........................................................169
19.8.16 Offset 09Ch: USB_BDT_PAGE1 – Buffer Descriptor Table Page Register #1...............169
19.8.17 Offset 0A0h: USB_FRAMEL – USB Frame Number Register Low...................................169
19.8.18 Offset 0A4h: USB_FRAMEH – USB Frame Number Register High .................................169
19.8.19 Offset 0A8h: USB_TOKEN – USB Token Register.............................................................170
19.8.20 Offset 0ACh: USB_SOFT – USB SOF Threshold Register .................................................170
19.8.21 Offset 0B4h: USB_BDT_PAGE2 – Buffer Descriptor Table Page Register #2 ...............170
19.8.22 Offset 0B8h: USB_BDT_PAGE3 – Buffer Descriptor Table Page Register #3 ...............170
19.8.23 USB_ENDPTn_CTRL – Endpoint “N” Control Registers ..................................................171
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