Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 80

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
9.3.4
9.3.5
DS0200-003
Offset 00Ch: MCR_FIFO – MCR FIFO Register
Offset 010h: MCR_ADC – MCR ADC Register
31:28
27:16
13:12
11:00
31:16
15:13
11:00
Bits
Bits
15
14
12
Type
Type
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
Reset
Reset
000h
000h
004h
000
00
0
0
0
0
1
Description
Reserved
Peak Amplitude (PEAK): In peak-detection mode, this provides the amplitude of the
peak. In Raw ADC mode, these bits are always 0.
Timeout (TO): In peak detection mode, indicates timeout (‘0’ = no timeout, ‘1’ =
timeout). In ADC mode, this bit is always ‘0’.
Peak Polarity (POL): In peak-detection mode, this provides the polarity of the peak
(‘0’ = negative peak, ‘1’ = positive peak). In Raw ADC mode, this bit is set to zero.
Track Number (TRACK):
information.
Delta-Time/ADC Sample (TIME):
sample.
Description
Reserved
ADC Reference Calibration (CAL): Selects the Peak to Peak differential input voltage
range for full-scale output.
MCR Reset (RST): When set, resets the MCR ADC.
ADC Clock Divider (DIV): Determines the divider for the ADC clock: See section
9.2.8.1 for details on how to create this value. Acceptable values:
 00: Track 0
 01: Track 1
 10: Track 2
 11: N/A
 000 = 0.50
 001 = 0.40
 010 = 0.30
 011 = 0.25
 100 = 0.20
 101 = 0.15
 110 = 0.10
 111 = 0.05
 000h: Illegal
 001h: hclk divided by 2
 002h: Illegal
 003h: Illegal
 004h: hclk divided by 5
 …
 FFFh: hclk divided by 256
Provides the track number associated with the FIFO
Contains the delta-time value or raw ADC
Page 67