Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 163
Z32AN00NW200SG
Manufacturer Part Number
Z32AN00NW200SG
Description
IC ARM922T MCU 200MHZ 256-BGA
Manufacturer
Zilog
Series
Encore!® 32r
Datasheet
1.Z32AN00NW200SG.pdf
(196 pages)
Specifications of Z32AN00NW200SG
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
Peripherals
DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
For Use With
269-4713 - KIT DEV ENCORE 32 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
269-4717
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Z32AN Series Data Sheet
18.9.2 Offset 04h: SPI_CTL – SPI Control Register
DS0200-003
31:08
Bits
07
06
05
04
03
02
01
00
Type
RW
RW
RW
RW
RW
RW
RW
RW
RO
Reset
0
0
0
0
0
0
0
0
0
Description
Reserved
Interrupt Request Enable (IRQE): When cleared, SPI interrupts are disabled. When
set, SPI interrupts are enabled. If transmit or receive DMA is enabled, the transmit data
complete interrupt is disabled, but other interrupt sources are enabled.
Start an SPI Interrupt Request (STR): When cleared, this value has no effect.
When set, sets SPI_STA.IRQ. This bit is cleared by writing 0 to this bit or clearing
SPI_STA.IRQ.
BRG Timer Interrupt Request (BIRQ): When cleared, if SPIEN = 0, disables the
Baud Rate Generation timer function. If SPIEN = 1, this bit has no effect. When set, if
SPIEN = 0, enables the Baud Rate Generation timer function and time-out interrupt. If
SPIEN = 1, this bit has no effect.
Phase Select (PHASE): Sets the phase relationship of the data to the clock (see
section 18.3).
Clock Polarity (CLKPOL):
transmission/reception.
Wire-OR (Open-Drain) Mode Enable (WOR): When set, all 4 SPI signal pins (nSS,
SCK, MISO, MOSI) configured for open-drain function. This typically used for multi-
master/ multi-slave configurations.
SPI Master Mode Enable (MMEN): When set, SPI is configured as a master. When
cleared, SPI is configured as a slave.
SPI Enable (SPIEN): When set, SPI operation is enabled.
When set, SCK idles to ‘1’ after character
Page 150
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