Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 91

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
10.3.1.8
10.3.1.9
DS0200-003
31:10
31:06
Offset 01Ch: SC_STATUS – Smart Card Interface VCC and Reset Status
Offset 024h: SC_SPIDMASEL – Smart Card DMA Channels and SPI Block Mapping
Bits
Bits
►Warning: Ensure that two Smart Card blocks do not map onto the same DMA channel as it can
lead to unpredictable operation.
09
08
07
06
05
04
03
02
01
00
05
04
03
02
01
00
Type
Type
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Description
Reserved
SIM4 Card Reset Status (SIM4_RESET): When set, reset is valid
SIM4 Card VCC Status (SIM4_VCC): When set, VCC is valid
SIM3 Card Reset Status (SIM3_ RESET): When set, Reset is valid
SIM3 Card VCC Status (SIM3_VCC): When set, VCC is valid
SIM2 Card Reset Status (SIM2_RESET): When set, Reset is valid
SIM2 Card VCC Status (SIM2_VCC): When set, VCC is valid
SIM1 Card Reset Status (SIM1_RESET): When set, Reset is valid
SIM1 Card VCC Status (SIM1_VCC): When set, VCC is valid
Main Card Reset Status (MAIN_RESET): When set, Reset is valid
Main Card VCC Status (MAIN_VCC): When set, VCC is valid
Description
Reserved
CS Reset (CSR): When set, before each SPI transfer all the Chip Selects will be High
for 2 hclk cycles.
CS Memory (CSM): When set, the chip select which are not addressed will keep the
same state as prior to SPI. That is, the 2 chip select can be asserted at the same time.
SC1 RX (SC1_RX): When set, selects SC1 RX for DMA
SC0 RX (SC0_RX): When set, selects SC0 RX for DMA
SC1 TX (SC1_TX): When set, selects SC1 TX for DMA
SC0 TX (SC0_TX): When set, selects SC0 TX for DMA
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