Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 25

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
3.5.2
DS0200-003
Offset 004h: PMUCLK – PMU Clock Control Register
29:25
23:17
15:08
07:05
04:00
Bits
31
30
24
16
Type
RW
RW
RW
RW
RW
RW
RO
RO
RO
Reset
00000
00h
0
0
0
0
0
0
0
DescriptionDS0200.docx
Crystal Disable (XTALDIS): When cleared, the crystal is disabled to put the device
into low power sleep mode. This bit is automatically cleared by wake up.
Source Clock Select (SRCCLKSEL): When cleared, select crystal clock as the source
clock. When set, select PLL clock as the source clock.
Reserved
USB Clock Divider (USBCLKDIV): When cleared, use HCLK. When set, use HCLK
divided by 2.
Reserved
External SDRAM Clock Enable (SDCLK): When cleared, SDCLK is disabled. When
set, SDCLK is enabled.
HCLK Divider (HCLKDIV): This specifies how much to divide fclk to produce hclk.
Reserved
FCLK Divider (FCLKDIV): This specifies how much to divide source clock to produce
fclk.
 00h: 1 (hclk = fclk)
 01h: 2 (hclk = fclk / 2)
 ...
 FFh: 256
 00000: 1 (fclk = source clock)
 00001: 2 (fclk = source clock / 2)
 ...
 11111: 32
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