Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 165

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
18.9.4 Offset 0Ch: SPI_MOD – SPI Mode Register
18.9.5 Offset 10h: SPI_DIAG – SPI Diagnostic State Register
DS0200-003
The register provides observability of internal SPI state.
31:07
05:02
31:08
05:00
Bits
Bits
06
01
00
07
06
Type
Type
RW
RW
RW
RW
RO
RO
RO
RO
RO
000000
Reset
Reset
0h
0
0
0
0
0
0
0
Description
Reserved
Diagnostic Mode Control (DIAG): For manufacturing test mode. Setting this bit
allows the Baud Rate Counter value to be read via the SPI_BRG. DIAG = 0 allows
reading of SPI_BRG to return the value in the SPI_BRG. When set, reading SPI_BRG
will return bits [15:0] of the SPI Baud Rate Counter.
Number of Data Bits per Character to Transfer (NUMBITS):
number of bits to shift for each character transfer. See SPI_DAT for information on
valid bit positions when the character length is less than 16-bits.
Slave Select I/O (SSIO): When cleared, nSS pin configured as an input. When set,
nSS pin configured as an output (Master Mode Only).
Slave Select Value (SSV): When cleared, if SSIO=1 and SPI is configured as a
master, asserts the active slow nSS pin to an external Slave. When set, if SSIO=1 and
SPI is configured as a master, de-asserts the active Low nSS pin to an external Slave.
Description
Reserved
Shift Clock Enable (SCKEN): When cleared, internal Shift Clock Enable is de-
asserted. When set, internal Shift Clock Enable is asserted (shift register will update
on the next hclk).
Transmit Clock Enable (TCKEN):
de-asserted. When set, internal transmit clock enable is asserted. When asserted, the
serial data out will update on the next hclk (MOSI or MISO).
SPI State Machine (SPISTATE): The current state of the internal SPI State Machine.
Value
0000
0001
0010
0011
0100
0101
0110
0111
Data Bits per Character
16
1
2
3
4
5
6
7
When cleared, internal transmit clock enable is
1000
1001
1010
1011
1100
1101
1110
1111
Bits
Data Bits per Character
10
11
12
13
14
15
8
9
Contains the
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