Z32AN00NW200SG Zilog, Z32AN00NW200SG Datasheet - Page 34

• Manufacturer Part Number: Z32AN00NW200SG
• Description: IC ARM922T MCU 200MHZ 256-BGA
• Manufacturer: Zilog
• Series: Encore!® 32r

Specifications of Z32AN00NW200SG

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, IrDA, SmartCard, SPI, UART/USART, USB OTG
• Peripherals: DMA, LCD, Magnetic Card Reader, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• For Use With: 269-4713 - KIT DEV ENCORE 32 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 269-4717

Z32AN Series Data Sheet
Chapter 6: Interrupt Controller (INTC)
6.1
6.2
DS0200-003
The interrupt controller is an APB device that prioritizes and routes all interrupt channels from internal
peripherals and external devices to the CPU. Features:
Interrupts are first fed into a Priority Encoder. The highest priority enabled interrupt is passed on to either the
IRQ or FIQ Processor. These are nearly identical and fully independent of each other – the INTC does not
prioritize FIQ delivery over IRQ delivery. These blocks pass interrupt requests to the CPU and provide the
proper vector when software reads the vector register. Additionally, the IRQ processor includes support for
interrupt nesting (interruption of ISRs).
Interrupt Channels and Sources
Interrupt Priority
Each interrupt channel can be assigned a priority level from 0 (highest) to 7 (lowest). This is done by
programming the INTC_CFGN. The interrupt priority level is only effective if the channel is configured as an
IRQ interrupt (not FIQ). All FIQ interrupts are considered to have a priority of 0.
The priority has two effects:






IRQ or FIQ generation for each interrupt source (programmable)
Unique vectors for each interrupt channel
Programmable priority for each channel (8 priority levels)
Support for nesting and preemption by higher priority interrupts (IRQ only)
If two or more enabled interrupts of the same type (IRQ/FIQ) arrive at the same time, the
higher priority interrupt will be serviced first. If two or more interrupts of the same priority arrive,
the interrupt with the lower channel number will have priority.
When using nested interrupts, only an interrupt of a higher programmed priority will generate a
new (nested) interrupt to the CPU. Interrupts of the same or lower priority are masked until the
CPU has indicated the completion of the ISR by writing to the INTC_IEND (or INTC_FEND for
FIQ)
#
0
1
2
3
4
5
6
7
Source
UART0
TMR6
TMR0
TMR1
TMR2
TMR3
TMR4
WDT
Table 6-1: Interrupt Source to Channel Mapping
10
11
12
13
14
15
#
8
9
SmartCard Alarm
SmartCard 0
SmartCard 1
GPIO0 A
GPIO0 B
GPIO1 A
GPIO1 B
Source
TMR5
16
18
20
21
22
23
17
19
#
Reserved
GPIO2 A
GPIO2 B
Source
DMAC
SPI0
MCR
ADC
USB
24
26
27
28
29
30
31
25
#
Reserved
Source
UART1
UART2
TMR7
TMR8
SPI1
RNG
RTC
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